A 1.5 GHz 90 nm embedded microprocessor core

Franco Ricci; Lawrence T. Clark; Tim Beatty; Wing Yu; Alex Bashmakov; Shay Demmons; Eric Fox; Jay Miller; Manish Biyani; Jon Haigh

doi:10.1109/VLSIC.2005.1469322

A 1.5 GHz 90 nm embedded microprocessor core

Franco Ricci, Lawrence T. Clark, Tim Beatty, Wing Yu, Alex Bashmakov, Shay Demmons, Eric Fox, Jay Miller, Manish Biyani, Jon Haigh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Scopus citations

Abstract

A 90 mn ARM™ V5TE compatible microprocessor core intended for high performance and low power embedded applications is described. The core includes an ECC protected 2^nd level 512 MB cache, high-bandwidth single-cycle L1 cache line fill and evict, and cache coherency. Circuit design for high speed and low power are described, as well as their impact on the micro-architecture. Features to support low standby power modes and embedded test are also described.

Original language	English (US)
Title of host publication	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages	12-15
Number of pages	4
Volume	2005
DOIs	https://doi.org/10.1109/VLSIC.2005.1469322
State	Published - 2005
Event	2005 Symposium on VLSI Circuits - Kyoto, Japan Duration: Jun 16 2005 → Jun 18 2005

Other

Other	2005 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	6/16/05 → 6/18/05

Keywords

Embedded and cache
Microprocessor
Power
VLSI

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/VLSIC.2005.1469322

Cite this

@inproceedings{844e1773efe74625b8143facc4adc3bc,

title = "A 1.5 GHz 90 nm embedded microprocessor core",

abstract = "A 90 mn ARM{\texttrademark} V5TE compatible microprocessor core intended for high performance and low power embedded applications is described. The core includes an ECC protected 2nd level 512 MB cache, high-bandwidth single-cycle L1 cache line fill and evict, and cache coherency. Circuit design for high speed and low power are described, as well as their impact on the micro-architecture. Features to support low standby power modes and embedded test are also described.",

keywords = "Embedded and cache, Microprocessor, Power, VLSI",

author = "Franco Ricci and Clark, {Lawrence T.} and Tim Beatty and Wing Yu and Alex Bashmakov and Shay Demmons and Eric Fox and Jay Miller and Manish Biyani and Jon Haigh",

year = "2005",

doi = "10.1109/VLSIC.2005.1469322",

language = "English (US)",

volume = "2005",

pages = "12--15",

booktitle = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

note = "2005 Symposium on VLSI Circuits ; Conference date: 16-06-2005 Through 18-06-2005",

}

TY - GEN

T1 - A 1.5 GHz 90 nm embedded microprocessor core

AU - Ricci, Franco

AU - Clark, Lawrence T.

AU - Beatty, Tim

AU - Yu, Wing

AU - Bashmakov, Alex

AU - Demmons, Shay

AU - Fox, Eric

AU - Miller, Jay

AU - Biyani, Manish

AU - Haigh, Jon

PY - 2005

Y1 - 2005

N2 - A 90 mn ARM™ V5TE compatible microprocessor core intended for high performance and low power embedded applications is described. The core includes an ECC protected 2nd level 512 MB cache, high-bandwidth single-cycle L1 cache line fill and evict, and cache coherency. Circuit design for high speed and low power are described, as well as their impact on the micro-architecture. Features to support low standby power modes and embedded test are also described.

AB - A 90 mn ARM™ V5TE compatible microprocessor core intended for high performance and low power embedded applications is described. The core includes an ECC protected 2nd level 512 MB cache, high-bandwidth single-cycle L1 cache line fill and evict, and cache coherency. Circuit design for high speed and low power are described, as well as their impact on the micro-architecture. Features to support low standby power modes and embedded test are also described.

KW - Embedded and cache

KW - Microprocessor

KW - Power

KW - VLSI

UR - http://www.scopus.com/inward/record.url?scp=33745167976&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33745167976&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2005.1469322

DO - 10.1109/VLSIC.2005.1469322

M3 - Conference contribution

AN - SCOPUS:33745167976

VL - 2005

SP - 12

EP - 15

BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

T2 - 2005 Symposium on VLSI Circuits

Y2 - 16 June 2005 through 18 June 2005

ER -

A 1.5 GHz 90 nm embedded microprocessor core

Abstract

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Keywords

ASJC Scopus subject areas

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