A 1.5 GHz 90 nm embedded microprocessor core

Franco Ricci, Lawrence T. Clark, Tim Beatty, Wing Yu, Alex Bashmakov, Shay Demmons, Eric Fox, Jay Miller, Manish Biyani, Jon Haigh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations

Abstract

A 90 mn ARM™ V5TE compatible microprocessor core intended for high performance and low power embedded applications is described. The core includes an ECC protected 2nd level 512 MB cache, high-bandwidth single-cycle L1 cache line fill and evict, and cache coherency. Circuit design for high speed and low power are described, as well as their impact on the micro-architecture. Features to support low standby power modes and embedded test are also described.

Original languageEnglish (US)
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Pages12-15
Number of pages4
Volume2005
DOIs
StatePublished - 2005
Event2005 Symposium on VLSI Circuits - Kyoto, Japan
Duration: Jun 16 2005Jun 18 2005

Other

Other2005 Symposium on VLSI Circuits
CountryJapan
CityKyoto
Period6/16/056/18/05

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Keywords

  • Embedded and cache
  • Microprocessor
  • Power
  • VLSI

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Ricci, F., Clark, L. T., Beatty, T., Yu, W., Bashmakov, A., Demmons, S., Fox, E., Miller, J., Biyani, M., & Haigh, J. (2005). A 1.5 GHz 90 nm embedded microprocessor core. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (Vol. 2005, pp. 12-15). [1469322] https://doi.org/10.1109/VLSIC.2005.1469322