A 1.5 GHz 90 nm embedded microprocessor core

Franco Ricci, Lawrence T. Clark, Tim Beatty, Wing Yu, Alex Bashmakov, Shay Demmons, Eric Fox, Jay Miller, Manish Biyani, Jon Haigh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations


A 90 mn ARM™ V5TE compatible microprocessor core intended for high performance and low power embedded applications is described. The core includes an ECC protected 2nd level 512 MB cache, high-bandwidth single-cycle L1 cache line fill and evict, and cache coherency. Circuit design for high speed and low power are described, as well as their impact on the micro-architecture. Features to support low standby power modes and embedded test are also described.

Original languageEnglish (US)
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Number of pages4
StatePublished - 2005
Event2005 Symposium on VLSI Circuits - Kyoto, Japan
Duration: Jun 16 2005Jun 18 2005


Other2005 Symposium on VLSI Circuits


  • Embedded and cache
  • Microprocessor
  • Power
  • VLSI

ASJC Scopus subject areas

  • Engineering(all)

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