Abstract
A radiation hardened by a design delay-locked loop (DLL) architecture for quadrature phase clock generation in a 133 MHz DDR memory designed on a foundry 0.13 μ m fabrication process is presented. The DLL employs an all-digital architecture, including a hardened digital integrator using error-correction logic. The area and power overhead due to the hardening are 32% and 37%, respectively. Simulation results demonstrate that the all-digital DLL is hardened against single-event transients with no timing impact due to hardening. Layout techniques to make the DLL hardened to multiple bit upsets are also presented.
Original language | English (US) |
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Article number | 5658008 |
Pages (from-to) | 3626-3633 |
Number of pages | 8 |
Journal | IEEE Transactions on Nuclear Science |
Volume | 57 |
Issue number | 6 PART 1 |
DOIs | |
State | Published - Dec 2010 |
Keywords
- Charge pump
- delay-locked loop (DLL)
- jitter phase-locked loop (PLL)
- single-event transients (SETs)
ASJC Scopus subject areas
- Nuclear and High Energy Physics
- Nuclear Energy and Engineering
- Electrical and Electronic Engineering