A 130-nm RHBD SRAM with high speed SET and area efficient TIP mitigation

Karl C. Mohr, Lawrence T. Clark, Keith Holbert

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

A radiation hardened by design 5 kB static random access memory appropriate for embedded system on a chip integrated circuits is presented. High speed dual redundant control logic suppresses single event transients, allowing 500 MHz operation. Dynamic supply modulation, reverse body bias, and array supply collapse are investigated, in place of annular layout, to suppress leakage current increases due to total ionizing dose effects. These approaches allow the use of two-edge NMOS transistor layout resulting in increased packing density. The design has been fabricated using a 130-nm bulk CMOS process; the parts were then tested and found to be functional. Experimental results from TID testing using a Co-60 gamma radiation source as well as heavy ion testing results are presented.

Original languageEnglish (US)
Pages (from-to)2092-2099
Number of pages8
JournalIEEE Transactions on Nuclear Science
Volume54
Issue number6
DOIs
StatePublished - Dec 2007

Fingerprint

Static random access storage
layouts
high speed
traveling ionospheric disturbances
systems-on-a-chip
packing density
random access memory
Testing
radiation sources
Heavy ions
Embedded systems
Leakage currents
Gamma rays
integrated circuits
logic
Integrated circuits
CMOS
heavy ions
Transistors
leakage

Keywords

  • Radiation hardening
  • Single event transient
  • Static random access memory
  • Total ionizing dose

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Nuclear Energy and Engineering

Cite this

A 130-nm RHBD SRAM with high speed SET and area efficient TIP mitigation. / Mohr, Karl C.; Clark, Lawrence T.; Holbert, Keith.

In: IEEE Transactions on Nuclear Science, Vol. 54, No. 6, 12.2007, p. 2092-2099.

Research output: Contribution to journalArticle

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