A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm

Amitesh Sridharan, Shaahin Angizi, Sai Kiran Cherupally, Fan Zhang, Jae Sun Seo, Deliang Fan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a generic and programmable Processing-in-SRAM (PSRAM) accelerator chip design based on an 8T-SRAM array to accommodate a complete set of Boolean logic operations (e.g., NOR/NAND/XOR, both 2- and 3-input), majority, and full adder, for the first time, all in a single cycle. PSRAM provides the programmability required for in-memory computing platforms that could be used for various applications such as parallel vector operation, neural networks, and data encryption. The prototype design is implemented in a SRAM macro with size of 16 kb, demonstrating one of the fastest programmable in-memory computing system to date operating at 1.23 GHz. The 65nm prototype chip achieves system-level peak throughput of 1.2 TOPS, and energy-efficiency of 34.98 TOPS/W at 1.2V.

Original languageEnglish (US)
Title of host publicationESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages153-156
Number of pages4
ISBN (Electronic)9781665484947
DOIs
StatePublished - 2022
Externally publishedYes
Event48th IEEE European Solid State Circuits Conference, ESSCIRC 2022 - Milan, Italy
Duration: Sep 19 2022Sep 22 2022

Publication series

NameESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings

Conference

Conference48th IEEE European Solid State Circuits Conference, ESSCIRC 2022
Country/TerritoryItaly
CityMilan
Period9/19/229/22/22

Keywords

  • In-memory computing (IMC)
  • programmability
  • SRAM

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Instrumentation
  • Artificial Intelligence

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