A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm

Amitesh Sridharan; Shaahin Angizi; Sai Kiran Cherupally; Fan Zhang; Jae Sun Seo; Deliang Fan

doi:10.1109/ESSCIRC55480.2022.9911440

A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm

Amitesh Sridharan, Shaahin Angizi, Sai Kiran Cherupally, Fan Zhang, Jae Sun Seo, Deliang Fan

Engineering, Ira A. Fulton Schools of (IAFSE)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

We present a generic and programmable Processing-in-SRAM (PSRAM) accelerator chip design based on an 8T-SRAM array to accommodate a complete set of Boolean logic operations (e.g., NOR/NAND/XOR, both 2- and 3-input), majority, and full adder, for the first time, all in a single cycle. PSRAM provides the programmability required for in-memory computing platforms that could be used for various applications such as parallel vector operation, neural networks, and data encryption. The prototype design is implemented in a SRAM macro with size of 16 kb, demonstrating one of the fastest programmable in-memory computing system to date operating at 1.23 GHz. The 65nm prototype chip achieves system-level peak throughput of 1.2 TOPS, and energy-efficiency of 34.98 TOPS/W at 1.2V.

Original language	English (US)
Title of host publication	ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	153-156
Number of pages	4
ISBN (Electronic)	9781665484947
DOIs	https://doi.org/10.1109/ESSCIRC55480.2022.9911440
State	Published - 2022
Event	48th IEEE European Solid State Circuits Conference, ESSCIRC 2022 - Milan, Italy Duration: Sep 19 2022 → Sep 22 2022

Publication series

Name	ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings

Conference

Conference	48th IEEE European Solid State Circuits Conference, ESSCIRC 2022
Country/Territory	Italy
City	Milan
Period	9/19/22 → 9/22/22

Keywords

In-memory computing (IMC)
programmability
SRAM

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Instrumentation
Artificial Intelligence

Access to Document

10.1109/ESSCIRC55480.2022.9911440

Cite this

Sridharan, A., Angizi, S., Cherupally, S. K., Zhang, F., Seo, J. S., & Fan, D. (2022). A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm. In ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings (pp. 153-156). (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ESSCIRC55480.2022.9911440

A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm. / Sridharan, Amitesh; Angizi, Shaahin; Cherupally, Sai Kiran et al.
ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. p. 153-156 (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sridharan, A, Angizi, S, Cherupally, SK, Zhang, F, Seo, JS & Fan, D 2022, A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm. in ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 153-156, 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022, Milan, Italy, 9/19/22. https://doi.org/10.1109/ESSCIRC55480.2022.9911440

Sridharan A, Angizi S, Cherupally SK, Zhang F, Seo JS, Fan D. A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm. In ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2022. p. 153-156. (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings). doi: 10.1109/ESSCIRC55480.2022.9911440

Sridharan, Amitesh ; Angizi, Shaahin ; Cherupally, Sai Kiran et al. / A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm. ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 153-156 (ESSCIRC 2022 - IEEE 48th European Solid State Circuits Conference, Proceedings).

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abstract = "We present a generic and programmable Processing-in-SRAM (PSRAM) accelerator chip design based on an 8T-SRAM array to accommodate a complete set of Boolean logic operations (e.g., NOR/NAND/XOR, both 2- and 3-input), majority, and full adder, for the first time, all in a single cycle. PSRAM provides the programmability required for in-memory computing platforms that could be used for various applications such as parallel vector operation, neural networks, and data encryption. The prototype design is implemented in a SRAM macro with size of 16 kb, demonstrating one of the fastest programmable in-memory computing system to date operating at 1.23 GHz. The 65nm prototype chip achieves system-level peak throughput of 1.2 TOPS, and energy-efficiency of 34.98 TOPS/W at 1.2V.",

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author = "Amitesh Sridharan and Shaahin Angizi and Cherupally, {Sai Kiran} and Fan Zhang and Seo, {Jae Sun} and Deliang Fan",

note = "Funding Information: ACKNOWLEDGEMENTS This work is supported in part by NSF grants 2003749 and 2144751, by SRC and DARPA. Publisher Copyright: {\textcopyright} 2022 IEEE.; 48th IEEE European Solid State Circuits Conference, ESSCIRC 2022 ; Conference date: 19-09-2022 Through 22-09-2022",

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AB - We present a generic and programmable Processing-in-SRAM (PSRAM) accelerator chip design based on an 8T-SRAM array to accommodate a complete set of Boolean logic operations (e.g., NOR/NAND/XOR, both 2- and 3-input), majority, and full adder, for the first time, all in a single cycle. PSRAM provides the programmability required for in-memory computing platforms that could be used for various applications such as parallel vector operation, neural networks, and data encryption. The prototype design is implemented in a SRAM macro with size of 16 kb, demonstrating one of the fastest programmable in-memory computing system to date operating at 1.23 GHz. The 65nm prototype chip achieves system-level peak throughput of 1.2 TOPS, and energy-efficiency of 34.98 TOPS/W at 1.2V.

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A 1.23-GHz 16-kb Programmable and Generic Processing-in-SRAM Accelerator in 65nm

Abstract

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Keywords

ASJC Scopus subject areas

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