TY - GEN
T1 - A 1.06 μw smart ECG processor in 65 nm CMOS for real-time biometrie authentication and personal cardiac monitoring
AU - Yin, Shihui
AU - Kim, Minkyu
AU - Kadetotad, Deepak
AU - Liu, Yang
AU - Bae, Chisung
AU - Kim, Sang Joon
AU - Cao, Yu
AU - Seo, Jae-sun
N1 - Publisher Copyright:
© 2017 JSAP.
PY - 2017/8/10
Y1 - 2017/8/10
N2 - A smart wearable electrocardiographic (ECG) processor is presented for secure ECG-based biometric authentication and cardiac monitoring, including arrhythmia and anomaly detection. Data-driven Lasso regression and low-precision techniques are developed to compress the neural networks by 24.4X. The prototype chip fabricated in 65 nm LP CMOS consumes 1.06 μW at 0.55 V for real-time ECG authentication. Equal error rates of 0.74% and 1.7% are achieved on ECG-ID database and in-house 645-subject database, respectively.
AB - A smart wearable electrocardiographic (ECG) processor is presented for secure ECG-based biometric authentication and cardiac monitoring, including arrhythmia and anomaly detection. Data-driven Lasso regression and low-precision techniques are developed to compress the neural networks by 24.4X. The prototype chip fabricated in 65 nm LP CMOS consumes 1.06 μW at 0.55 V for real-time ECG authentication. Equal error rates of 0.74% and 1.7% are achieved on ECG-ID database and in-house 645-subject database, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85032174335&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85032174335&partnerID=8YFLogxK
U2 - 10.23919/VLSIC.2017.8008563
DO - 10.23919/VLSIC.2017.8008563
M3 - Conference contribution
AN - SCOPUS:85032174335
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - C102-C103
BT - 2017 Symposium on VLSI Circuits, VLSI Circuits 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 31st Symposium on VLSI Circuits, VLSI Circuits 2017
Y2 - 5 June 2017 through 8 June 2017
ER -