A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction

Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, Nan Sun

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Abstract

This paper presents a power-efficient SNR enhancement technique for SAR ADCs. By accurately estimating the conversion residue, it can suppress both comparator noise and quantization error. Thus, it allows the use of a noisy low-power comparator and a relatively low resolution DAC to achieve high resolution. The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the LSB comparisons. A prototype ADC is designed in 65nm CMOS. Its SNR is improved by 7dB with the proposed technique. Overall, it achieves 10.5-b ENOB while operating at 100kS/s and consuming 645nW from a 0.7V power supply.

Original languageEnglish (US)
Title of host publication2015 IEEE Custom Integrated Circuits Conference, CICC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479986828
DOIs
StatePublished - Nov 25 2015
Externally publishedYes
EventIEEE Custom Integrated Circuits Conference, CICC 2015 - San Jose, United States
Duration: Sep 28 2015Sep 30 2015

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2015-November
ISSN (Print)0886-5930

Other

OtherIEEE Custom Integrated Circuits Conference, CICC 2015
Country/TerritoryUnited States
CitySan Jose
Period9/28/159/30/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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