Abstract

Digital low-dropout (DLDO) regulators are gaining attention due to their design scalability for distributed multiple voltage domain applications required in state-of-the-art system-on-chips. Due to the discrete nature of the output current and the discrete-time control loop, the steady-state response of the DLDO has inherent output voltage ripple. A hybrid DLDO (HD-LDO) with fast response and stable operation across a wide load range while reducing the output voltage ripple is proposed. In the HD-LDO, a DLDO and a low current analog ripple cancelation amplifier (RCA) work in parallel. The output dc of the RCA is sensed by a 2-bit analog-to-digital converter, and the digitized linear stage current is fed into the DLDO as an error signal. During load transients, a gear-shift controller enables fast transient response using dynamic load estimation. The DLDO suppresses the output dc of the RCA within its current resolution. With this arrangement, a majority of the dc load current is provided by the DLDO and the RCA supplies ripple cancelation current. The HD-LDO is designed and fabricated in a 180-nm CMOS technology, and occupies 0.697 mm2 of the die area. The HD-LDO operates with an input voltage range of 1.43-2.0 V and an output voltage range of 1.0-1.57 V. At 100-mA load current, the HD-LDO achieves a current peak efficiency of 99.11% and a settling time of 15 clock periods with a 0.5-MHz clock for a current switching between 10 and 90 mA. The RCA suppresses fundamental, second, and third harmonics of the switching frequency by 13.7, 13.3, and 14.1 dB, respectively.

Original languageEnglish (US)
Article number7548368
Pages (from-to)696-704
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number2
DOIs
StatePublished - Feb 1 2017

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Electric potential
Clocks
Switching frequency
Digital to analog conversion
Dynamic loads
Transient analysis
Gears
Scalability
Controllers
System-on-chip

Keywords

  • Digital low-dropout (DLDO) regulator
  • hybrid DLDO (HD-LDO)
  • LDO regulator
  • low ripple DLDO
  • Ripple cancelation amplifier (RCA)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

A 100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO with Active Ripple Suppression. / Cheah, Michael; Mandal, Debashis; Bakkaloglu, Bertan; Kiaei, Sayfe.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 2, 7548368, 01.02.2017, p. 696-704.

Research output: Contribution to journalArticle

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abstract = "Digital low-dropout (DLDO) regulators are gaining attention due to their design scalability for distributed multiple voltage domain applications required in state-of-the-art system-on-chips. Due to the discrete nature of the output current and the discrete-time control loop, the steady-state response of the DLDO has inherent output voltage ripple. A hybrid DLDO (HD-LDO) with fast response and stable operation across a wide load range while reducing the output voltage ripple is proposed. In the HD-LDO, a DLDO and a low current analog ripple cancelation amplifier (RCA) work in parallel. The output dc of the RCA is sensed by a 2-bit analog-to-digital converter, and the digitized linear stage current is fed into the DLDO as an error signal. During load transients, a gear-shift controller enables fast transient response using dynamic load estimation. The DLDO suppresses the output dc of the RCA within its current resolution. With this arrangement, a majority of the dc load current is provided by the DLDO and the RCA supplies ripple cancelation current. The HD-LDO is designed and fabricated in a 180-nm CMOS technology, and occupies 0.697 mm2 of the die area. The HD-LDO operates with an input voltage range of 1.43-2.0 V and an output voltage range of 1.0-1.57 V. At 100-mA load current, the HD-LDO achieves a current peak efficiency of 99.11{\%} and a settling time of 15 clock periods with a 0.5-MHz clock for a current switching between 10 and 90 mA. The RCA suppresses fundamental, second, and third harmonics of the switching frequency by 13.7, 13.3, and 14.1 dB, respectively.",
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