A 10-GHz Frequency Divider Using Selectively Doped Heterostructure Transistors

R. H. Hendel, S. S. Pei, Richard Kiehl, C. W. Tu, M. D. Feuer, R. Dingle

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

We report the first complementary clocked frequency divider using dual gate selectively doped heterostructure transistors(SDHT's). The circuit employs a master-slave flip-flop design which consists of four direct coupled AND-NOR gates. The nominal gate length and the gate-gate, separation in the dual gate SDHT's are 1 μm. A maximum dividing frequency of 10.1 GHz at 77 K was achieved; at this frequency the circuit dissipated 49.9 mW at 1.67-V bias. This is the highest operating frequency reported for static frequency dividers at any temperature. At room temperature the dividers were operated successfully at frequencies up to 5.5 GHz with a total power dissipation of 34.8 mW at 1.97-V bias. The lowest speed-power product at room temperature was obtained at 5 GHz with 14.9-mW power dissipation at 1.45-V bias.

Original languageEnglish (US)
Pages (from-to)406-408
Number of pages3
JournalIEEE Electron Device Letters
Volume5
Issue number10
DOIs
StatePublished - 1984
Externally publishedYes

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Heterojunctions
Transistors
Energy dissipation
Networks (circuits)
Flip flop circuits
Temperature

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Engineering(all)

Cite this

A 10-GHz Frequency Divider Using Selectively Doped Heterostructure Transistors. / Hendel, R. H.; Pei, S. S.; Kiehl, Richard; Tu, C. W.; Feuer, M. D.; Dingle, R.

In: IEEE Electron Device Letters, Vol. 5, No. 10, 1984, p. 406-408.

Research output: Contribution to journalArticle

Hendel, R. H. ; Pei, S. S. ; Kiehl, Richard ; Tu, C. W. ; Feuer, M. D. ; Dingle, R. / A 10-GHz Frequency Divider Using Selectively Doped Heterostructure Transistors. In: IEEE Electron Device Letters. 1984 ; Vol. 5, No. 10. pp. 406-408.
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