Abstract
We report the first complementary clocked frequency divider using dual gate selectively doped heterostructure transistors(SDHT's). The circuit employs a master-slave flip-flop design which consists of four direct coupled AND-NOR gates. The nominal gate length and the gate-gate, separation in the dual gate SDHT's are 1 μm. A maximum dividing frequency of 10.1 GHz at 77 K was achieved; at this frequency the circuit dissipated 49.9 mW at 1.67-V bias. This is the highest operating frequency reported for static frequency dividers at any temperature. At room temperature the dividers were operated successfully at frequencies up to 5.5 GHz with a total power dissipation of 34.8 mW at 1.97-V bias. The lowest speed-power product at room temperature was obtained at 5 GHz with 14.9-mW power dissipation at 1.45-V bias.
Original language | English (US) |
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Pages (from-to) | 406-408 |
Number of pages | 3 |
Journal | IEEE Electron Device Letters |
Volume | 5 |
Issue number | 10 |
DOIs | |
State | Published - Oct 1984 |
Externally published | Yes |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering