A 1 MHz bandwidth, 6 GHz 0.18 μm CMOS type-I δσ fractional-N synthesizer for WiMAX applications

Hiva Hedayati, Waleed Khalil, Bertan Bakkaloglu

Research output: Contribution to journalArticlepeer-review

40 Scopus citations

Abstract

A 6 GHz Type-I fractional-N PLL with noise-cancelling DAC and discrete-time sample and hold loop-filter is presented. The 1 MHz bandwidth PLL utilizes an inherently linear PFD and noise-cancelling charge-pump DAC circuit to reduce quantization noise by more than 25 dB. The worst case near-integer in-band spur is measured at -61 dBc and the integrated RMS phase error is -42 dBc. The measured in-band phase noise at 300 kHz offset from the 6.12 GHz carrier is -102 dBc/Hz and out-of-band phase noise at 3 MHz offset is -130 dBc/Hz. The PLL loop settling time for an accuracy of 0.01 ppm and a frequency step of 60 MHz is less than 11 μs. The synthesizer is fabricated in a 0.18 μm CMOS technology with 6 metal layers and consumes 26 mA from a 1.8 V power supply.

Original languageEnglish (US)
Article number5342360
Pages (from-to)3244-3252
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number12
DOIs
StatePublished - Dec 1 2009

Keywords

  • Fractional-N synthesizer
  • Phase-locked loop (PLL)
  • Quantization noise
  • Sigma-delta modulator
  • Wideband

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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