A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS

Long Chen, Kareem Ragab, Xiyuan Tang, Jeonggoo Song, Arindam Sanyal, Nan Sun

Research output: Contribution to journalArticlepeer-review

19 Scopus citations

Abstract

This brief presents a low-power and high-speed single-channel successive approximation register (SAR) analogto- digital converter (ADC). It uses a loop-unrolled architecture with multiple comparators. Each comparator is used not only to make a comparison but also to store its output and generate an asynchronous clock to trigger the next comparator. The SAR logic is significantly simplified to increase speed and reduce power. The comparator offset and decision time are optimized with a bidirectional single-side switching technique by controlling the input common-mode voltage Vcm. To remove the nonlinearity due to the comparators' offset mismatch, a simple and effective Vcm-adaptive offset calibration technique is proposed. The prototype ADC in 40-nm CMOS achieves a 35-dB signal to noiseplus- distortion ratio and a 48-dB spurious-free dynamic range at a 700-MS/s sampling rate. It consumes 0.95 mW, leading to a Walden figure-of-merit (FOM) of 30 fJ/conversion-step and a Schreier FOM of 153.4 dB.

Original languageEnglish (US)
Article number7460902
Pages (from-to)244-248
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume64
Issue number3
DOIs
StatePublished - Mar 2017
Externally publishedYes

Keywords

  • Analog-to-digital converter (ADC)
  • high speed
  • offset calibration
  • successive approximation register (SAR)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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