A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining

Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester

Research output: Chapter in Book/Report/Conference proceedingConference contribution

56 Scopus citations

Abstract

Recently, aggressive voltage scaling was shown as an important technique in achieving highly energy-efficient circuits. Specifically, scaling V dd to near or sub-threshold regions was proposed for energy-constrained sensor systems to enable long lifetime and small system volume [1][2][4]. However, energy efficiency degrades below a certain voltage, Vmin, due to rapidly increasing leakage energy consumption, setting a fundamental limit on the achievable energy efficiency. In addition, voltage scaling degrades performance and heightens delay variability due to large I d sensitivity to PVT variations in the ultra-low voltage (ULV) regime. This paper uses circuit and architectural methods to further reduce the minimum energy point, or Emin, and establish a new lower limit on energy efficiency, while simultaneously improving performance and robustness. The approaches are demonstrated on an FFT core in 65nm CMOS.

Original languageEnglish (US)
Title of host publication2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
Pages342-343
Number of pages2
DOIs
StatePublished - May 12 2011
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
Duration: Feb 20 2011Feb 24 2011

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Other

Other2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
CountryUnited States
CitySan Francisco, CA
Period2/20/112/24/11

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Seok, M., Jeon, D., Chakrabarti, C., Blaauw, D., & Sylvester, D. (2011). A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining. In 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011 (pp. 342-343). [5746346] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2011.5746346