A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining

Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester

Research output: Chapter in Book/Report/Conference proceedingConference contribution

56 Citations (Scopus)

Abstract

Recently, aggressive voltage scaling was shown as an important technique in achieving highly energy-efficient circuits. Specifically, scaling V dd to near or sub-threshold regions was proposed for energy-constrained sensor systems to enable long lifetime and small system volume [1][2][4]. However, energy efficiency degrades below a certain voltage, Vmin, due to rapidly increasing leakage energy consumption, setting a fundamental limit on the achievable energy efficiency. In addition, voltage scaling degrades performance and heightens delay variability due to large I d sensitivity to PVT variations in the ultra-low voltage (ULV) regime. This paper uses circuit and architectural methods to further reduce the minimum energy point, or Emin, and establish a new lower limit on energy efficiency, while simultaneously improving performance and robustness. The approaches are demonstrated on an FFT core in 65nm CMOS.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages342-343
Number of pages2
DOIs
StatePublished - 2011
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
Duration: Feb 20 2011Feb 24 2011

Other

Other2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
CountryUnited States
CitySan Francisco, CA
Period2/20/112/24/11

Fingerprint

Fast Fourier transforms
Energy efficiency
Networks (circuits)
Electric potential
Energy utilization
Sensors
Voltage scaling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Seok, M., Jeon, D., Chakrabarti, C., Blaauw, D., & Sylvester, D. (2011). A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 342-343). [5746346] https://doi.org/10.1109/ISSCC.2011.5746346

A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining. / Seok, Mingoo; Jeon, Dongsuk; Chakrabarti, Chaitali; Blaauw, David; Sylvester, Dennis.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2011. p. 342-343 5746346.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Seok, M, Jeon, D, Chakrabarti, C, Blaauw, D & Sylvester, D 2011, A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference., 5746346, pp. 342-343, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, San Francisco, CA, United States, 2/20/11. https://doi.org/10.1109/ISSCC.2011.5746346
Seok M, Jeon D, Chakrabarti C, Blaauw D, Sylvester D. A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2011. p. 342-343. 5746346 https://doi.org/10.1109/ISSCC.2011.5746346
Seok, Mingoo ; Jeon, Dongsuk ; Chakrabarti, Chaitali ; Blaauw, David ; Sylvester, Dennis. / A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2011. pp. 342-343
@inproceedings{f88280f534844cf382a835090e467a66,
title = "A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining",
abstract = "Recently, aggressive voltage scaling was shown as an important technique in achieving highly energy-efficient circuits. Specifically, scaling V dd to near or sub-threshold regions was proposed for energy-constrained sensor systems to enable long lifetime and small system volume [1][2][4]. However, energy efficiency degrades below a certain voltage, Vmin, due to rapidly increasing leakage energy consumption, setting a fundamental limit on the achievable energy efficiency. In addition, voltage scaling degrades performance and heightens delay variability due to large I d sensitivity to PVT variations in the ultra-low voltage (ULV) regime. This paper uses circuit and architectural methods to further reduce the minimum energy point, or Emin, and establish a new lower limit on energy efficiency, while simultaneously improving performance and robustness. The approaches are demonstrated on an FFT core in 65nm CMOS.",
author = "Mingoo Seok and Dongsuk Jeon and Chaitali Chakrabarti and David Blaauw and Dennis Sylvester",
year = "2011",
doi = "10.1109/ISSCC.2011.5746346",
language = "English (US)",
isbn = "9781612843001",
pages = "342--343",
booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

}

TY - GEN

T1 - A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining

AU - Seok, Mingoo

AU - Jeon, Dongsuk

AU - Chakrabarti, Chaitali

AU - Blaauw, David

AU - Sylvester, Dennis

PY - 2011

Y1 - 2011

N2 - Recently, aggressive voltage scaling was shown as an important technique in achieving highly energy-efficient circuits. Specifically, scaling V dd to near or sub-threshold regions was proposed for energy-constrained sensor systems to enable long lifetime and small system volume [1][2][4]. However, energy efficiency degrades below a certain voltage, Vmin, due to rapidly increasing leakage energy consumption, setting a fundamental limit on the achievable energy efficiency. In addition, voltage scaling degrades performance and heightens delay variability due to large I d sensitivity to PVT variations in the ultra-low voltage (ULV) regime. This paper uses circuit and architectural methods to further reduce the minimum energy point, or Emin, and establish a new lower limit on energy efficiency, while simultaneously improving performance and robustness. The approaches are demonstrated on an FFT core in 65nm CMOS.

AB - Recently, aggressive voltage scaling was shown as an important technique in achieving highly energy-efficient circuits. Specifically, scaling V dd to near or sub-threshold regions was proposed for energy-constrained sensor systems to enable long lifetime and small system volume [1][2][4]. However, energy efficiency degrades below a certain voltage, Vmin, due to rapidly increasing leakage energy consumption, setting a fundamental limit on the achievable energy efficiency. In addition, voltage scaling degrades performance and heightens delay variability due to large I d sensitivity to PVT variations in the ultra-low voltage (ULV) regime. This paper uses circuit and architectural methods to further reduce the minimum energy point, or Emin, and establish a new lower limit on energy efficiency, while simultaneously improving performance and robustness. The approaches are demonstrated on an FFT core in 65nm CMOS.

UR - http://www.scopus.com/inward/record.url?scp=79955746511&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79955746511&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2011.5746346

DO - 10.1109/ISSCC.2011.5746346

M3 - Conference contribution

AN - SCOPUS:79955746511

SN - 9781612843001

SP - 342

EP - 343

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

ER -