A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI

Yong Liu, Ping Hsuan Hsieh, Seongwon Kim, Jae Sun Seo, Robert Montoye, Leland Chang, Jose Tierno, Daniel Friedman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Scopus citations

Abstract

Compact low-power signaling schemes to drive on-chip interconnects are needed for processor chips where high-bandwidth data buses connect processor cores and on-chip cache. Since a significant portion of the signaling power is dynamic power spent on driving long wires, reducing the signal swing improves power efficiency [1-3]. In addition, charge-recycling techniques reduce signal swing by stacking circuits with regular and predictable data switching activities, such as logic circuits [4] and clocking circuits [5]. Unlike conventional schemes, low-swing I/O that leverages charge-recycling techniques offers the potential for quadratic power reduction. We present a compact low-power I/O for on-chip signaling using charge-recycling stacked drivers and compact voltage regulators/converters. A receiver circuit modified from a parametric amplifier-based design [6] further improves the area and power efficiency.

Original languageEnglish (US)
Title of host publication2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers
Pages400-401
Number of pages2
DOIs
StatePublished - Apr 29 2013
Externally publishedYes
Event2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, CA, United States
Duration: Feb 17 2013Feb 21 2013

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume56
ISSN (Print)0193-6530

Other

Other2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
CountryUnited States
CitySan Francisco, CA
Period2/17/132/21/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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