A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI

Yong Liu, Ping Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert Montoye, Leland Chang, Jose Tierno, Daniel Friedman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

Compact low-power signaling schemes to drive on-chip interconnects are needed for processor chips where high-bandwidth data buses connect processor cores and on-chip cache. Since a significant portion of the signaling power is dynamic power spent on driving long wires, reducing the signal swing improves power efficiency [1-3]. In addition, charge-recycling techniques reduce signal swing by stacking circuits with regular and predictable data switching activities, such as logic circuits [4] and clocking circuits [5]. Unlike conventional schemes, low-swing I/O that leverages charge-recycling techniques offers the potential for quadratic power reduction. We present a compact low-power I/O for on-chip signaling using charge-recycling stacked drivers and compact voltage regulators/converters. A receiver circuit modified from a parametric amplifier-based design [6] further improves the area and power efficiency.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages400-401
Number of pages2
Volume56
DOIs
StatePublished - 2013
Externally publishedYes
Event2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, CA, United States
Duration: Feb 17 2013Feb 21 2013

Other

Other2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
CountryUnited States
CitySan Francisco, CA
Period2/17/132/21/13

Fingerprint

Recycling
Networks (circuits)
Parametric amplifiers
Voltage regulators
Logic circuits
Wire
Bandwidth

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Liu, Y., Hsieh, P. H., Kim, S., Seo, J., Montoye, R., Chang, L., ... Friedman, D. (2013). A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 56, pp. 400-401). [6487787] https://doi.org/10.1109/ISSCC.2013.6487787

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. / Liu, Yong; Hsieh, Ping Hsuan; Kim, Seongwon; Seo, Jae-sun; Montoye, Robert; Chang, Leland; Tierno, Jose; Friedman, Daniel.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 56 2013. p. 400-401 6487787.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Liu, Y, Hsieh, PH, Kim, S, Seo, J, Montoye, R, Chang, L, Tierno, J & Friedman, D 2013, A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 56, 6487787, pp. 400-401, 2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013, San Francisco, CA, United States, 2/17/13. https://doi.org/10.1109/ISSCC.2013.6487787
Liu Y, Hsieh PH, Kim S, Seo J, Montoye R, Chang L et al. A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 56. 2013. p. 400-401. 6487787 https://doi.org/10.1109/ISSCC.2013.6487787
Liu, Yong ; Hsieh, Ping Hsuan ; Kim, Seongwon ; Seo, Jae-sun ; Montoye, Robert ; Chang, Leland ; Tierno, Jose ; Friedman, Daniel. / A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 56 2013. pp. 400-401
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