A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI

Yong Liu; Ping Hsuan Hsieh; Seongwon Kim; Jae Sun Seo; Robert Montoye; Leland Chang; Jose Tierno; Daniel Friedman

doi:10.1109/ISSCC.2013.6487787

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI

Yong Liu, Ping Hsuan Hsieh, Seongwon Kim, Jae Sun Seo, Robert Montoye, Leland Chang, Jose Tierno, Daniel Friedman

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

18 Scopus citations

Abstract

Compact low-power signaling schemes to drive on-chip interconnects are needed for processor chips where high-bandwidth data buses connect processor cores and on-chip cache. Since a significant portion of the signaling power is dynamic power spent on driving long wires, reducing the signal swing improves power efficiency [1-3]. In addition, charge-recycling techniques reduce signal swing by stacking circuits with regular and predictable data switching activities, such as logic circuits [4] and clocking circuits [5]. Unlike conventional schemes, low-swing I/O that leverages charge-recycling techniques offers the potential for quadratic power reduction. We present a compact low-power I/O for on-chip signaling using charge-recycling stacked drivers and compact voltage regulators/converters. A receiver circuit modified from a parametric amplifier-based design [6] further improves the area and power efficiency.

Original language	English (US)
Title of host publication	2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers
Pages	400-401
Number of pages	2
DOIs	https://doi.org/10.1109/ISSCC.2013.6487787
State	Published - Apr 29 2013
Externally published	Yes
Event	2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, CA, United States Duration: Feb 17 2013 → Feb 21 2013

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	56
ISSN (Print)	0193-6530

Other

Other	2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
Country/Territory	United States
City	San Francisco, CA
Period	2/17/13 → 2/21/13

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2013.6487787

Cite this

Liu, Y., Hsieh, P. H., Kim, S., Seo, J. S., Montoye, R., Chang, L., Tierno, J., & Friedman, D. (2013). A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. In 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers (pp. 400-401). [6487787] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 56). https://doi.org/10.1109/ISSCC.2013.6487787

A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. / Liu, Yong; Hsieh, Ping Hsuan; Kim, Seongwon et al.

2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. 2013. p. 400-401 6487787 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 56).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Liu, Y, Hsieh, PH, Kim, S, Seo, JS, Montoye, R, Chang, L, Tierno, J & Friedman, D 2013, A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. in 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers., 6487787, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 56, pp. 400-401, 2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013, San Francisco, CA, United States, 2/17/13. https://doi.org/10.1109/ISSCC.2013.6487787

Liu Y, Hsieh PH, Kim S, Seo JS, Montoye R, Chang L et al. A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI. In 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers. 2013. p. 400-401. 6487787. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2013.6487787

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abstract = "Compact low-power signaling schemes to drive on-chip interconnects are needed for processor chips where high-bandwidth data buses connect processor cores and on-chip cache. Since a significant portion of the signaling power is dynamic power spent on driving long wires, reducing the signal swing improves power efficiency [1-3]. In addition, charge-recycling techniques reduce signal swing by stacking circuits with regular and predictable data switching activities, such as logic circuits [4] and clocking circuits [5]. Unlike conventional schemes, low-swing I/O that leverages charge-recycling techniques offers the potential for quadratic power reduction. We present a compact low-power I/O for on-chip signaling using charge-recycling stacked drivers and compact voltage regulators/converters. A receiver circuit modified from a parametric amplifier-based design [6] further improves the area and power efficiency.",

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AB - Compact low-power signaling schemes to drive on-chip interconnects are needed for processor chips where high-bandwidth data buses connect processor cores and on-chip cache. Since a significant portion of the signaling power is dynamic power spent on driving long wires, reducing the signal swing improves power efficiency [1-3]. In addition, charge-recycling techniques reduce signal swing by stacking circuits with regular and predictable data switching activities, such as logic circuits [4] and clocking circuits [5]. Unlike conventional schemes, low-swing I/O that leverages charge-recycling techniques offers the potential for quadratic power reduction. We present a compact low-power I/O for on-chip signaling using charge-recycling stacked drivers and compact voltage regulators/converters. A receiver circuit modified from a parametric amplifier-based design [6] further improves the area and power efficiency.

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A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI

Abstract

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