A 0.13 μm low-power race-free programmable logic array

Giby Samson, Lawrence T. Clark

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A PLA using NAND and NOR gates for the AND and OR logic planes, respectively, is described. The circuit design, timing and power advantages are described. Nearly 50% power savings over a conventional PLA design is achieved on a 130 nm process at less than 10% delay cost. The new PLA circuit has been fabricated on a 130 nm low standby power process and tested silicon operates at 905 MHz at VDD = 1.5 V.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Pages313-316
Number of pages4
DOIs
StatePublished - Dec 1 2006
EventIEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States
Duration: Sep 10 2006Sep 13 2006

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

OtherIEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Country/TerritoryUnited States
CitySan Jose, CA
Period9/10/069/13/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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