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  • Jae-sun Seo
2020

Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks

Yin, S., Jiang, Z., Kim, M., Gupta, T., Seok, M. & Seo, J. S., Jan 2020, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28, 1, p. 48-61 14 p., 8867863.

Research output: Contribution to journalArticle

2019

A 1.06-μW Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring

Yin, S., Kim, M., Kadetotad, D., Liu, Y., Bae, C., Kim, S. J., Cao, Y. & Seo, J. S., Aug 1 2019, In : IEEE Journal of Solid-State Circuits. 54, 8, p. 2316-2326 11 p., 8713394.

Research output: Contribution to journalArticle

A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity with All Parameters Stored On-Chip

Kadetotad, D., Berisha, V., Chakrabarti, C. & Seo, J. S., Sep 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., p. 119-122 4 p. 8902809. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A Real-Time 17-Scale Object Detection Accelerator with Adaptive 2000-Stage Classification in 65 nm CMOS

Kim, M., Mohanty, A., Kadetotad, D., Wei, L., He, X., Cao, Y. & Seo, J. S., Oct 2019, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 66, 10, p. 3843-3853 11 p., 8741167.

Research output: Contribution to journalArticle

C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing

Jiang, Z., Yin, S., Seo, J. S. & Seok, M., Sep 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., p. 131-134 4 p. 8902752. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cases for analog mixed signal computing integrated circuits for deep neural networks

Seok, M., Yang, M., Jiang, Z., Lazar, A. A. & Seo, J., Apr 1 2019, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8742044. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Corrigendum: Large-scale neuromorphic spiking array processors: A quest to mimic the brain (Frontiers in Neuroscience (2018) 12 (891) DOI: 10.3389/fnins.2018.00891)

Thakur, C. S., Molin, J. L., Cauwenberghs, G., Indiveri, G., Kumar, K., Qiao, N., Schemmel, J., Wang, R., Chicca, E., Hasler, J. O., Seo, J., Yu, S., Cao, Y., Van Schaik, A. & Etienne-Cummings, R., Jan 1 2019, In : Frontiers in Neuroscience. 13, JAN, 991.

Research output: Contribution to journalComment/debate

Open Access

Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview

Chen, C. Y., Murmann, B., Seo, J. & Yoo, H. J., Jun 1 2019, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 9, 2, p. 247-252 6 p., 8720273.

Research output: Contribution to journalArticle

1 Scopus citations

ECG authentication neural network hardware design with collective optimization of low precision and structured compression

Cherupally, S. K., Srivastava, G., Yin, S., Kadetotad, D., Bae, C., Kim, S. J. & Jae-Sun, S., Jan 1 2019, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 8702308. (Proceedings - IEEE International Symposium on Circuits and Systems; vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Inference engine benchmarking across technological platforms from CMOS to RRAM

Peng, X., Kim, M., Sun, X., Yin, S., Rakshit, T., Hatcher, R. M., Kittl, J. A., Seo, J. S. & Yu, S., Sep 30 2019, MEMSYS 2019 - Proceedings of the International Symposium on Memory Systems. Association for Computing Machinery, p. 471-479 9 p. (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks

Srivastava, G., Kadetotad, D., Yin, S., Berisha, V., Chakrabarti, C. & Seo, J. S., May 1 2019, 2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 1393-1397 5 p. 8682791. (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings; vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM

Saikia, J., Yin, S., Jiang, Z., Seok, M. & Seo, J. S., Jul 2019, International Symposium on Low Power Electronics and Design, ISLPED 2019. Institute of Electrical and Electronics Engineers Inc., 8824822. (Proceedings of the International Symposium on Low Power Electronics and Design; vol. 2019-July).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Monolithically Integrated RRAM- And CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning

Yin, S., Seo, J. S., Kim, Y., Han, X., Barnaby, H., Yu, S., Luo, Y., He, W., Sun, X. & Kim, J. J., Nov 1 2019, In : IEEE Micro. 39, 6, p. 54-63 10 p., 8894568.

Research output: Contribution to journalArticle

Neuromorphic hardware accelerator for SNN inference based on STT-RAM crossbar arrays

Kulkarni, S. R., Kadetotad, D. V., Yin, S., Seo, J. S. & Rajendran, B., Nov 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019. Institute of Electrical and Electronics Engineers Inc., p. 438-441 4 p. 8964886. (2019 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2018

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler

Ma, Y., Suda, N., Cao, Y., Vrudhula, S. & Seo, J., Jan 1 2018, (Accepted/In press) In : Integration, the VLSI Journal.

Research output: Contribution to journalArticle

18 Scopus citations

Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations

Yin, S., Venkataramanaiah, S. K., Chen, G. K., Krishnamurthy, R., Cao, Y., Chakrabarti, C. & Seo, J., Mar 23 2018, 2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1-4 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs

Ma, Y., Zheng, T., Cao, Y., Vrudhula, S. & Seo, J., Nov 5 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., a57

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks

Yin, S., Sun, X., Yu, S., Seo, J. & Chakrabarti, C., Dec 31 2018, Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2018. Institute of Electrical and Electronics Engineers Inc., p. 13-18 6 p. 8598445. (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons

Sun, X., Peng, X., Chen, P. Y., Liu, R., Seo, J. & Yu, S., Feb 20 2018, ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 574-579 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations

Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms

Basu, A., Chang, M. F., Chicca, E., Karnik, T., Li, H. & Seo, J., Mar 1 2018, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 8, 1, p. 1-5 5 p.

Research output: Contribution to journalEditorial

Guest editors' introduction: Frontiers of hardware and algorithms for on-chip learning

Cao, Y., Li, X., Seo, J. & Dasika, G., Jul 1 2018, In : ACM Journal on Emerging Technologies in Computing Systems. 14, 2, 3205944.

Research output: Contribution to journalEditorial

Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions

Basu, A., Acharya, J., Karnik, T., Liu, H., Li, H., Seo, J. & Song, C., Mar 14 2018, (Accepted/In press) In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Research output: Contribution to journalArticle

14 Scopus citations

Minimizing area and energy of deep learning hardware design using collective low precision and structured compression

Yin, S., Srivastava, G., Venkataramanaiah, S. K., Chakrabarti, C., Berisha, V. & Seo, J., Apr 10 2018, Conference Record of 51st Asilomar Conference on Signals, Systems and Computers, ACSSC 2017. Matthews, M. B. (ed.). Institute of Electrical and Electronics Engineers Inc., Vol. 2017-October. p. 1907-1911 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
25 Scopus citations

Process Scalability of Pulse-Based Circuits for Analog Image Convolution

D'Angelo, R., Du, X., Salthouse, C. D., Hollosi, B., Freifeld, G., Uy, W., Huang, H., Tran, N., Chery, A., Seo, J., Cao, Y., Poppe, D. C. & Sonkusale, S. R., Apr 19 2018, (Accepted/In press) In : IEEE Transactions on Circuits and Systems I: Regular Papers.

Research output: Contribution to journalArticle

Random sparse adaptation for accurate inference with inaccurate multi-level RRAM arrays

Mohanty, A., Du, X., Chen, P. Y., Seo, J., Yu, S. & Cao, Y., Jan 23 2018, 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., Vol. Part F134366. p. 6.3.1-6.3.4

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Towards a Wearable Cough Detector Based on Neural Networks

Kadambi, P., Mohanty, A., Ren, H., Smith, J., McGuinnes, K., Holt, K., Furtwaengler, A., Slepetys, R., Yang, Z., Seo, J., Chae, J., Cao, Y. & Berisha, V., Sep 10 2018, 2018 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-April. p. 2161-2165 5 p. 8461394

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Well-Posed Verilog-A Compact Model for Phase Change Memory

Kulkarni, S. R., Kadetotad, D. V., Seo, J. & Rajendran, B., Nov 28 2018, SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-September. p. 369-373 5 p. 8551667

Research output: Chapter in Book/Report/Conference proceedingConference contribution

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks

Sun, X., Yin, S., Peng, X., Liu, R., Seo, J. & Yu, S., Apr 19 2018, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1423-1428 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Scopus citations

XNOR-SRAM: In-memory computing SRAM macro for binary/ternary deep neural networks

Jiang, Z., Yin, S., Seok, M. & Seo, J., Oct 25 2018, 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-June. p. 173-174 2 p. 8510687

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Scopus citations
2017

A 1.06 μw smart ECG processor in 65 nm CMOS for real-time biometrie authentication and personal cardiac monitoring

Yin, S., Kim, M., Kadetotad, D., Liu, Y., Bae, C., Kim, S. J., Cao, Y. & Seo, J., Aug 10 2017, 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., p. C102-C103 8008563

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks

Ma, Y., Cao, Y., Vrudhula, S. & Seo, J., Oct 2 2017, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers Inc., 8056824

Research output: Chapter in Book/Report/Conference proceedingConference contribution

36 Scopus citations

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS

Kim, M., Mohanty, A., Kadetotad, D., Suda, N., Wei, L., Saseendran, P., He, X., Cao, Y. & Seo, J., Sep 25 2017, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050798

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS

Kim, M., Mohanty, A., Kadetotad, D., Suda, N., Wei, L., Saseendran, P., He, X., Cao, Y. & Seo, J., Feb 16 2017, 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., p. 21-22 2 p. 7858282

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Bi-Level rare temporal pattern detection

Zhou, D., He, J., Cao, Y. & Seo, J., Jan 31 2017, Proceedings - 16th IEEE International Conference on Data Mining, ICDM 2016. Institute of Electrical and Electronics Engineers Inc., p. 719-728 10 p. 7837896

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Comprehensive evaluation of openCL-based CNN implementations for FPGAs

Tapiador-Morales, R., Rios-Navarro, A., Linares-Barranco, A., Kim, M., Kadetotad, D. & Seo, J., 2017, Advances in Computational Intelligence - 14th International Work-Conference on Artificial Neural Networks, IWANN 2017, Proceedings. Springer Verlag, Vol. 10306 LNCS. p. 271-282 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10306 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Designing ECG-based physical unclonable function for security of wearable devices

Yin, S., Bae, C., Kim, S. J. & Seo, J., Sep 13 2017, 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society: Smarter Technology for a Healthier World, EMBC 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 3509-3512 4 p. 8037613

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

End-to-end scalable FPGA accelerator for deep residual networks

Ma, Y., Kim, M., Cao, Y., Vrudhula, S. & Seo, J., Sep 25 2017, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050344

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Scopus citations

Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators

Mi, X., Moghadam, H. F. & Seo, J., May 11 2017, Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc., p. 1269-1272 4 p. 7927186

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Improving efficiency in sparse learning with the feedforward inhibitory motif

Xu, Z., Skorheim, S., Tu, M., Berisha, V., Yu, S., Seo, J., Bazhenov, M. & Cao, Y., Feb 11 2017, (Accepted/In press) In : Neurocomputing.

Research output: Contribution to journalArticle

Low-power neuromorphic speech recognition engine with coarse-grain sparsity

Yin, S., Kadetotad, D., Yan, B., Song, C., Chen, Y., Chakrabarti, C. & Seo, J., Feb 16 2017, 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., p. 111-114 4 p. 7858305

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition

Chang, K., Kadetotad, D., Cao, Y., Seo, J. & Lim, S. K., Aug 11 2017, ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 8009175

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Optimizing loop operation and dataflow in FPGA acceleration of deep convolutional neural networks

Ma, Y., Cao, Y., Vrudhula, S. & Seo, J., Feb 22 2017, FPGA 2017 - Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. Association for Computing Machinery, Inc, p. 45-54 10 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

94 Scopus citations

Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities

Li, J., Seo, J., Kymissis, I. & Seok, M., Oct 1 2017, In : IEEE Journal of Solid-State Circuits. 52, 10, p. 2550-2562 13 p., 8030042.

Research output: Contribution to journalArticle

9 Scopus citations

Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability

Li, J., Seo, J., Kymissis, I. & Seok, M., Feb 6 2017, 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 289-292 4 p. 7844192

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2016

A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware

Shah, M., Arunachalam, S., Wang, J., Blaauw, D., Sylvester, D., Kim, H. S., Seo, J. & Chakrabarti, C., Nov 25 2016, (Accepted/In press) In : Journal of Signal Processing Systems. p. 1-15 15 p.

Research output: Contribution to journalArticle

4 Scopus citations