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  • Yu Cao
2012

Design benchmarking to 7nm with FinFET predictive technology models

Sinha, S., Cline, B., Yeric, G., Chandra, V. & Cao, Y., Sep 4 2012, ISLPED'12 - Proceedings of the International Symposium on Low Power Electronics and Design. p. 15-20 6 p. (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

24 Scopus citations
2011

A drift-diffusion model of pinned photodiode enabling opto-electronic circuit simulation

Su, Y., Wang, L., Lin, X., He, J., Zhao, X., Cao, Y., Zhang, D. & Li, Y., Nov 23 2011, Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011. p. 682-685 4 p. (Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A TDC-based test platform for dynamic circuit aging characterization

Chen, M., Reddy, V., Carulli, J., Krishnan, S., Rentala, V., Srinivasan, V. & Cao, Y., Jun 23 2011, 2011 International Reliability Physics Symposium, IRPS 2011. p. 2B.2.1-2B.2.5 5784448. (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations
2017

Cost-Effective Design Solutions for Enhancing PRAM Reliability and Performance

Yang, C., Mao, M., Cao, Y. & Chakrabarti, C., Jan 1 2017, In : IEEE Transactions on Multi-Scale Computing Systems. 3, 1, p. 1-11 11 p., 7422141.

Research output: Contribution to journalArticle

1 Scopus citations
2011

FinFET reliability issue analysis by forward gated-diode method

Liu, Z., Yu, C., Ma, C., Wu, W., Wang, W., Wang, R. & He, J., Nov 23 2011, Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011. p. 168-171 4 p. (Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

A workload-aware neuromorphic controller for dynamic power and thermal management

Sinha, S., Suh, J., Bakkaloglu, B. & Cao, Y., Sep 1 2011, Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2011. p. 200-207 8 p. 5963936. (Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2011).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2012

Aging statistics based on trapping/detrapping: Silicon evidence, modeling and long-term prediction

Velamala, J. B., Sutaria, K. B., Sato, T. & Cao, Y., Sep 28 2012, 2012 IEEE International Reliability Physics Symposium, IRPS 2012. p. 2F.2.1-2F.2.5 6241795. (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

36 Scopus citations
2013

Compact modeling of parameter variations of nanoscale CMOS due to random dopant fluctuation

Ye, Y., Zhu, Y., He, H., Mei, J., Cao, Y. & He, J., Aug 9 2013, Technical Proceedings of the 2013 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2013. p. 552-555 4 p. (Technical Proceedings of the 2013 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2013; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2017

Adaptive accelerated aging with 28nm HKMG technology

Patra, D., Reza, A. K., Hassan, M. K., Katoozi, M., Cannon, E. H., Roy, K. & Cao, Y., May 30 2017, 2017 International Reliability Physics Symposium, IRPS 2017. Institute of Electrical and Electronics Engineers Inc., p. CR2.1-CR2.4 7936351

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2014

BTI-induced aging under random stress waveforms: Modeling, simulation and silicon validation

Sutaria, K., Ramkumar, A., Zhu, R., Rajveev, R., Ma, Y. & Cao, Y., Jan 1 2014, DAC 2014 - 51st Design Automation Conference, Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2593101. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations
2011

Correlation of no trouble found errors to negative bias temperature instability

LiVolsi, R., McCormick, K., Torres, M., Velamala, J., Zheng, R. & Cao, Y., May 13 2011, 2011 Aerospace Conference, AERO 2011. 5747585. (IEEE Aerospace Conference Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2014

Charge trapping in MOSFETS: BTI and RTN modeling for circuits

Wirth, G., Cao, Y., Velamala, J. B., Sutaria, K. B. & Sato, T., Jul 1 2014, Bias Temperature Instability for Devices and Circuits. Springer New York, p. 751-782 32 p.

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Scopus citations

Low cost ECC schemes for improving the reliability of DRAM+PRAMMAIN memory systems

Mao, M., Yang, C., Xu, Z., Cao, Y. & Chakrabarti, C., Dec 15 2014, IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation. Institute of Electrical and Electronics Engineers Inc., 6986076. (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2011

Analytic potential model for asymmetricunderlap gate-all-around MOSFET

Wang, S., Guo, X., Zhang, L., Zhang, C., Liu, Z., Wang, G., Zhang, Y., Wu, W., Zhao, X., Wang, W., Cao, Y., Ye, Y., Wang, R., Ma, Y. & He, J., Nov 23 2011, Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011. p. 776-779 4 p. (Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2020

GAR: Graph assisted reasoning for object detection

Li, Z., Du, X. & Cao, Y., Mar 2020, Proceedings - 2020 IEEE Winter Conference on Applications of Computer Vision, WACV 2020. Institute of Electrical and Electronics Engineers Inc., p. 1284-1293 10 p. 9093559. (Proceedings - 2020 IEEE Winter Conference on Applications of Computer Vision, WACV 2020).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2013

Junctionless nanowire MOSFET with dynamic threshold voltage operation methodology

Mei, J., Zhang, A., Yu, C., Ye, Y., Wang, H., Deng, W. & He, J., Aug 9 2013, Technical Proceedings of the 2013 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2013. p. 516-519 4 p. (Technical Proceedings of the 2013 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2013; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Analytic model foramorphous GST OTS in phase change memory cell with hopping transport

Wang, W., Wang, C., Cao, Y., Wang, H., Ye, Y. & He, J., Aug 9 2013, Technical Proceedings of the 2013 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2013. p. 508-511 4 p. (Technical Proceedings of the 2013 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2013; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2017

TDDB in HfSiON/SiO2 dielectric stack: Büttiker probe based NEGF modeling, prediction and experiment

Reza, A. K., Hassan, M. K., Roy, K., Patra, D., Bansal, A. & Cao, Y., May 30 2017, 2017 International Reliability Physics Symposium, IRPS 2017. Institute of Electrical and Electronics Engineers Inc., p. DG5.1-DG5.6 7936362

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations
2015

Circuit design for reliability

Reis, R., Wirth, G. & Cao, Y., Jan 1 2015, Springer New York. 272 p.

Research output: Book/ReportBook

17 Scopus citations
2018

Accelerated BTI degradation under stochastic TDDB effect

Patra, D., Reza, A. K., Katoozi, M., Cannon, E. H., Roy, K. & Cao, Y., May 25 2018, 2018 IEEE International Reliability Physics Symposium, IRPS 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-March. p. 5C.51-5C.54

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations
2016

High-performance radio frequency transistors based on diameter-separated semiconducting carbon nanotubes

Cao, Y., Che, Y., Seo, J. W. T., Gui, H., Hersam, M. C. & Zhou, C., Jun 6 2016, In : Applied Physics Letters. 108, 23, 233105.

Research output: Contribution to journalArticle

12 Scopus citations
2011

An efficient iterative grid selection strategy for time-mapped harmonic balance method

Xu, Z., Zhuang, H., Jiang, B., Gu, B., Lin, X., He, J., Cao, Y., Zhang, Y., Wang, G., Deng, P., Zhao, X., Zhang, Y., Ma, Y., Wu, W. & Wang, W., 2011, Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011. p. 671-674 4 p. (Technical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011; vol. 2).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2014

Cross-layer modeling and simulation of circuit reliability

Cao, Y., Velamala, J., Sutaria, K., Chen, M. S. W., Ahlbin, J., Esqueda, I. S., Bajura, M. & Fritze, M., Jan 1 2014, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33, 1, p. 8-23 16 p., 6685855.

Research output: Contribution to journalArticle

32 Scopus citations

Screen printing as a scalable and low-cost approach for rigid and flexible thin-film transistors using separated carbon nanotubes

Cao, X., Chen, H., Gu, X., Liu, B., Wang, W., Cao, Y., Wu, F. & Zhou, C., Dec 23 2014, In : ACS nano. 8, 12, p. 12769-12776 8 p.

Research output: Contribution to journalArticle

104 Scopus citations
2011

Self-tuning for maximized lifetime energy-efficiency in the presence of circuit aging

Mintarno, E., Skaf, J., Zheng, R., Velamala, J. B., Cao, Y., Boyd, S., Dutton, R. W. & Mitra, S., May 1 2011, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 5, p. 760-773 14 p., 5752409.

Research output: Contribution to journalArticle

70 Scopus citations
2016

Carbon Nanotube Macroelectronics for Active Matrix Polymer-Dispersed Liquid Crystal Displays

Cong, S., Cao, Y., Fang, X., Wang, Y., Liu, Q., Gui, H., Shen, C., Cao, X., Kim, E. S. & Zhou, C., Nov 22 2016, In : ACS Nano. 10, 11, p. 10068-10074 7 p.

Research output: Contribution to journalArticle

19 Scopus citations
2017

RTN in Scaled Transistors for On-Chip Random Seed Generation

Mohanty, A., Sutaria, K. B., Awano, H., Sato, T. & Cao, Y., Apr 12 2017, (Accepted/In press) In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Research output: Contribution to journalArticle

3 Scopus citations
2012

Variation-aware supply voltage assignment for simultaneous power and aging optimization

Chen, X., Wang, Y., Cao, Y., Ma, Y. & Yang, H., Jan 1 2012, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 11, p. 2143-2147 5 p., 6042352.

Research output: Contribution to journalArticle

20 Scopus citations
2016

Radio frequency transistors based on ultra-high purity semiconducting carbon nanotubes with superior extrinsic maximum oscillation frequency

Cao, Y., Che, Y., Gui, H., Cao, X. & Zhou, C., Feb 1 2016, In : Nano Research. 9, 2, p. 363-371 9 p.

Research output: Contribution to journalArticle

17 Scopus citations
2015

Finite-point method for efficient timing characterization of sequential elements

Subramaniam, A. R., Roveda, J. & Cao, Y., Mar 1 2015, In : Integration, the VLSI Journal. 49, p. 104-113 10 p.

Research output: Contribution to journalArticle

2014

A pinned photodiode analytic model enabling opto-electronic circuit simulation

Zhu, H., Shi, M., Su, Y., Zhao, X., Chen, Q., Yu, C., He, J., Wang, H., Ye, Y. & He, H., Feb 1 2014, In : Journal of Computational and Theoretical Nanoscience. 11, 2, p. 313-317 5 p.

Research output: Contribution to journalArticle

1 Scopus citations
2013

Numerical electron mobility model of nanoscale symmetric, asymmetric and independent double-gate MOSFETs

He, J., Xu, Y., Chen, L., Zhang, L., Zhou, X., Ma, C., Cao, Y., Ye, Y., Wang, C., Liang, H. & Chan, M., Apr 1 2013, In : Journal of Computational and Theoretical Nanoscience. 10, 4, p. 763-771 9 p.

Research output: Contribution to journalArticle

2012

Exploring sub-20nm FinFET design with predictive technology models

Sinha, S., Yeric, G., Chandra, V., Cline, B. & Cao, Y., Jul 11 2012, Proceedings of the 49th Annual Design Automation Conference, DAC '12. p. 283-288 6 p. (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

208 Scopus citations
2011

Statistical modeling and simulation of threshold variation under random dopant fluctuations and line-edge roughness

Ye, Y., Liu, F., Chen, M., Nassif, S. & Cao, Y., Jun 1 2011, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 6, p. 987-996 10 p., 5439902.

Research output: Contribution to journalArticle

50 Scopus citations
2019

Towards efficient neural networks on-a-chip: Joint hardware-algorithm approaches

Du, X., Krishnan, G., Mohanty, A., Li, Z., Charan, G. & Cao, Y., Mar 2019, China Semiconductor Technology International Conference 2019, CSTIC 2019. Claeys, C., Huang, R., Wu, H., Lin, Q., Liang, S., Song, P., Guo, Z., Lai, K., Zhang, Y., Qu, X., Lung, H-L. & Yu, W. (eds.). Institute of Electrical and Electronics Engineers Inc., 8755608. (China Semiconductor Technology International Conference 2019, CSTIC 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2015

Accelerated aging in analog and digital circuits with feedback

Sutaria, K. B., Mohanty, A., Wang, R., Huang, R. & Cao, Y., Sep 1 2015, In : IEEE Transactions on Device and Materials Reliability. 15, 3, p. 384-393 10 p., 7159040.

Research output: Contribution to journalArticle

12 Scopus citations
2011

Workload-aware neuromorphic design of the power controller

Sinha, S., Suh, J., Bakkaloglu, B. & Cao, Y., Sep 1 2011, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 1, 3, p. 381-390 10 p., 6035994.

Research output: Contribution to journalArticle

9 Scopus citations
2015

A finite-point method for efficient gate characterization under multiple input switching

Subramaniam, A. R., Roveda, J. & Cao, Y., Nov 1 2015, In : ACM Transactions on Design Automation of Electronic Systems. 21, 1, 10.

Research output: Contribution to journalArticle

2016

A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation

Suda, N., Suh, J., Hakim, N., Cao, Y. & Bakkaloglu, B., Jan 25 2016, (Accepted/In press) In : IEEE Transactions on Circuits and Systems I: Regular Papers.

Research output: Contribution to journalArticle

9 Scopus citations
2015

Parallel architecture with resistive crosspoint array for dictionary learning acceleration

Kadetotad, D., Xu, Z., Mohanty, A., Chen, P. Y., Lin, B., Ye, J., Vrudhula, S., Yu, S., Cao, Y. & Seo, J., Jun 1 2015, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 5, 2, p. 194-204 11 p., 07116611.

Research output: Contribution to journalArticle

33 Scopus citations
2017

Improving efficiency in sparse learning with the feedforward inhibitory motif

Xu, Z., Skorheim, S., Tu, M., Berisha, V., Yu, S., Seo, J., Bazhenov, M. & Cao, Y., Dec 6 2017, In : Neurocomputing. 267, p. 141-151 11 p.

Research output: Contribution to journalArticle

2014

Parallel programming of resistive cross-point array for synaptic plasticity

Xu, Z., Mohanty, A., Chen, P. Y., Kadetotad, D., Lin, B., Ye, J., Vrudhula, S., Yu, S., Seo, J. & Cao, Y., 2014, Procedia Computer Science. Elsevier, Vol. 41. p. 126-133 8 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations
2017

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS

Kim, M., Mohanty, A., Kadetotad, D., Suda, N., Wei, L., Saseendran, P., He, X., Cao, Y. & Seo, J., Feb 16 2017, 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., p. 21-22 2 p. 7858282

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations
2015

Technological exploration of RRAM crossbar array for matrix-vector multiplication

Gu, P., Li, B., Tang, T., Yu, S., Cao, Y., Wang, Y. & Yang, H., Mar 11 2015, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., p. 106-111 6 p. 7058989. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

38 Scopus citations
2018
2 Scopus citations
2016

Ranking the parameters of deep neural networks using the fisher information

Tu, M., Berisha, V., Woolf, M., Seo, J. & Cao, Y., May 18 2016, 2016 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-May. p. 2647-2651 5 p. 7472157

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations
2017

A 1.06 μw smart ECG processor in 65 nm CMOS for real-time biometrie authentication and personal cardiac monitoring

Yin, S., Kim, M., Kadetotad, D., Liu, Y., Bae, C., Kim, S. J., Cao, Y. & Seo, J., Aug 10 2017, 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., p. C102-C103 8008563. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations
2015

On-chip sparse learning with resistive cross-point array architecture

Yu, S. & Cao, Y., May 20 2015, Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. Association for Computing Machinery, Vol. 20-22-May-2015. p. 195-197 3 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations
2017

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS

Kim, M., Mohanty, A., Kadetotad, D., Suda, N., Wei, L., Saseendran, P., He, X., Cao, Y. & Seo, J., Sep 25 2017, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050798

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2016

Mitigating effects of non-ideal synaptic device characteristics for on-chip learning

Chen, P. Y., Lin, B., Wang, I. T., Hou, T. H., Ye, J., Vrudhula, S., Seo, J., Cao, Y. & Yu, S., Jan 5 2016, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., p. 194-199 6 p. 7372570. (2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

82 Scopus citations