9-Bit time-digital-converter-assisted compressive-sensing analogue-digitalconverter with 4 GS/s equivalent speed

B. Hu, Fengbo Ren, Z. Z. Chen, X. Jiang, M. C F Chang

Research output: Contribution to journalArticle

Abstract

A novel 9-bit time-digital-converter (TDC)-assisted analogue-digitalconverter (ADC) supporting energy-efficient high-speed compressivesensing (CS) operation is presented. With a voltage-time-converter serving as the cross-domain residue conveyer, the proposed twostage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation (SAR) ADC frontend and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS-enabled sub-Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal-noise-distortion-ratio (SNDR) and a figure-of-merit (FOM) of 101 fJ/conversion step.

Original languageEnglish (US)
Pages (from-to)430-432
Number of pages3
JournalElectronics Letters
Volume52
Issue number6
DOIs
StatePublished - Mar 17 2016

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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9-Bit time-digital-converter-assisted compressive-sensing analogue-digitalconverter with 4 GS/s equivalent speed. / Hu, B.; Ren, Fengbo; Chen, Z. Z.; Jiang, X.; Chang, M. C F.

In: Electronics Letters, Vol. 52, No. 6, 17.03.2016, p. 430-432.

Research output: Contribution to journalArticle

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