9-Bit time-digital-converter-assisted compressive-sensing analogue-digitalconverter with 4 GS/s equivalent speed

B. Hu; Fengbo Ren; Z. Z. Chen; X. Jiang; M. C F Chang

doi:10.1049/el.2015.3778

9-Bit time-digital-converter-assisted compressive-sensing analogue-digitalconverter with 4 GS/s equivalent speed

B. Hu, Fengbo Ren, Z. Z. Chen, X. Jiang, M. C F Chang

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

A novel 9-bit time-digital-converter (TDC)-assisted analogue-digitalconverter (ADC) supporting energy-efficient high-speed compressivesensing (CS) operation is presented. With a voltage-time-converter serving as the cross-domain residue conveyer, the proposed twostage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation (SAR) ADC frontend and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS-enabled sub-Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal-noise-distortion-ratio (SNDR) and a figure-of-merit (FOM) of 101 fJ/conversion step.

Original language	English (US)
Pages (from-to)	430-432
Number of pages	3
Journal	Electronics Letters
Volume	52
Issue number	6
DOIs	https://doi.org/10.1049/el.2015.3778
State	Published - Mar 17 2016

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el.2015.3778

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title = "9-Bit time-digital-converter-assisted compressive-sensing analogue-digitalconverter with 4 GS/s equivalent speed",

abstract = "A novel 9-bit time-digital-converter (TDC)-assisted analogue-digitalconverter (ADC) supporting energy-efficient high-speed compressivesensing (CS) operation is presented. With a voltage-time-converter serving as the cross-domain residue conveyer, the proposed twostage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation (SAR) ADC frontend and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS-enabled sub-Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal-noise-distortion-ratio (SNDR) and a figure-of-merit (FOM) of 101 fJ/conversion step.",

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AU - Ren, Fengbo

AU - Chen, Z. Z.

AU - Jiang, X.

AU - Chang, M. C F

N1 - Publisher Copyright: © The Institution of Engineering and Technology 2016.

PY - 2016/3/17

Y1 - 2016/3/17

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AB - A novel 9-bit time-digital-converter (TDC)-assisted analogue-digitalconverter (ADC) supporting energy-efficient high-speed compressivesensing (CS) operation is presented. With a voltage-time-converter serving as the cross-domain residue conveyer, the proposed twostage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation (SAR) ADC frontend and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS-enabled sub-Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal-noise-distortion-ratio (SNDR) and a figure-of-merit (FOM) of 101 fJ/conversion step.

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9-Bit time-digital-converter-assisted compressive-sensing analogue-digitalconverter with 4 GS/s equivalent speed

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