A novel 9-bit time-digital-converter (TDC)-assisted analogue-digitalconverter (ADC) supporting energy-efficient high-speed compressivesensing (CS) operation is presented. With a voltage-time-converter serving as the cross-domain residue conveyer, the proposed twostage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation (SAR) ADC frontend and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS-enabled sub-Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal-noise-distortion-ratio (SNDR) and a figure-of-merit (FOM) of 101 fJ/conversion step.
|Original language||English (US)|
|Number of pages||3|
|State||Published - Mar 17 2016|
ASJC Scopus subject areas
- Electrical and Electronic Engineering