8.6fJ/step VCO-Based CT 2nd-Order ΔΣ ADC

Akshay Jayaraj, Abhijit Das, Srinivas Arcot, Arindam Sanyal

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A purely VCO-based continuous-time (CT), single-loop second-order ΔΣ ADC is proposed in this work. Two ring oscillators are used as integrators to perform second-order quantization noise shaping. The proposed CT ADC does not require additional circuit for excess loop delay compensation. A current-reuse DAC architecture is proposed to simultaneously reduce ADC noise and power consumption. A 65nm prototype consumes 105 μW from 1V supply at sampling frequency of 32.6MHz, and achieves a walden FoM of 8.6fJ/step over 2.3MHz bandwidth, which is the best among current CT ΔΣ ADCs.

Original languageEnglish (US)
Title of host publicationProceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages197-200
Number of pages4
ISBN (Electronic)9781728151069
DOIs
StatePublished - Nov 2019
Externally publishedYes
Event15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 - Macao, China
Duration: Nov 4 2019Nov 6 2019

Publication series

NameProceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Conference

Conference15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019
Country/TerritoryChina
CityMacao
Period11/4/1911/6/19

Keywords

  • analog-to-digital converter
  • continuous-time ADC
  • delta-sigma
  • voltage-controlled oscillator

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

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