TY - JOUR
T1 - 76-dB DR, 48 fJ/Step Second-Order VCO-Based Current-to-Digital Converter
AU - Jayaraj, Akshay
AU - Danesh, Mohammadhadi
AU - Chandrasekaran, Sanjeev Tannirkulam
AU - Sanyal, Arindam
N1 - Funding Information:
Manuscript received May 15, 2019; revised August 21, 2019; accepted September 12, 2019. Date of publication October 15, 2019; date of current version April 1, 2020. This work was supported by the Semiconductor Research Corporation (SRC) through The University of Texas at Dallas’ Texas Analog Center of Excellence (TxACE) under Grant 2712.020. This article was recommended by Associate Editor J. Fernandes. (Corresponding author: Akshay Jayaraj.) The authors are with the Department of Electrical Engineering, University at Buffalo, Buffalo, NY 14260 USA (e-mail: akshayja@buffalo.edu; mdanesh@buffalo.edu; stannirk@buffalo.edu; arindams@buffalo.edu).
Funding Information:
This work was supported by the Semiconductor Research Corporation (SRC) through The University of Texas at Dallas' Texas Analog Center of Excellence (TxACE) under Grant 2712.020.
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2020/4
Y1 - 2020/4
N2 - A continuous-time (CT) second-order Δ Σ current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator which results in significant power and noise reduction compared to previous prototype. Excess loop delay in the proposed CDC is countered through judicious selection of loop parameters and no auxiliary DAC is used for loop delay compensation. A prototype CDC is implemented in 65nm CMOS and achieves 76dB dynamic range at a bandwidth of 0.2MHz from 1V supply with a walden FoM of 48fJ/step which is 9× improvement on the state-of-the-art.
AB - A continuous-time (CT) second-order Δ Σ current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator which results in significant power and noise reduction compared to previous prototype. Excess loop delay in the proposed CDC is countered through judicious selection of loop parameters and no auxiliary DAC is used for loop delay compensation. A prototype CDC is implemented in 65nm CMOS and achieves 76dB dynamic range at a bandwidth of 0.2MHz from 1V supply with a walden FoM of 48fJ/step which is 9× improvement on the state-of-the-art.
KW - Voltage controlled oscillator (VCO)
KW - continuous-time ΔΣ
KW - current-reuse
KW - current-to-digital converter
KW - noise shaping
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U2 - 10.1109/TCSI.2019.2941956
DO - 10.1109/TCSI.2019.2941956
M3 - Article
AN - SCOPUS:85082882762
SN - 1549-8328
VL - 67
SP - 1149
EP - 1157
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 4
M1 - 8869919
ER -