76-dB DR, 48 fJ/Step Second-Order VCO-Based Current-to-Digital Converter

Akshay Jayaraj, Mohammadhadi Danesh, Sanjeev Tannirkulam Chandrasekaran, Arindam Sanyal

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

A continuous-time (CT) second-order Δ Σ current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator which results in significant power and noise reduction compared to previous prototype. Excess loop delay in the proposed CDC is countered through judicious selection of loop parameters and no auxiliary DAC is used for loop delay compensation. A prototype CDC is implemented in 65nm CMOS and achieves 76dB dynamic range at a bandwidth of 0.2MHz from 1V supply with a walden FoM of 48fJ/step which is 9× improvement on the state-of-the-art.

Original languageEnglish (US)
Article number8869919
Pages (from-to)1149-1157
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume67
Issue number4
DOIs
StatePublished - Apr 2020
Externally publishedYes

Keywords

  • continuous-time ΔΣ
  • current-reuse
  • current-to-digital converter
  • noise shaping
  • Voltage controlled oscillator (VCO)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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