3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation

Shimeng Yu, Hong Yu Chen, Yexin Deng, Bin Gao, Zizhen Jiang, Jinfeng Kang, H. S Philip Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

33 Citations (Scopus)

Abstract

3D vertical RRAM scaling limit is investigated. 3D RRAM functionality along with a viable write/read scheme for the 3D array are experimentally demonstrated for the first time, using plane electrode with thickness (t m) down to 5 nm to minimize 3D stack height. Through 3D circuit simulation of the write/read margin, we conclude the practical lower bound for the lithographic half-pitch, F, is 26 nm for tm=5 nm and isolation SiO2 thickness of 6 nm, assuming a trench etching aspect ratio of 30. This is equivalent to 0.09F2/bit. Although a 2D array can scale further to F=13 nm, 3D array device density is 11× higher than a 2D array with the same number of bits (16kb). Shrinking tm is more effective for increasing integration density than shrinking F for a 3D array. To enlarge 3D array partition size, it is necessary to replace the commonly used TiN with lower resistivity electrode materials.

Original languageEnglish (US)
Title of host publicationDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - 2013
Externally publishedYes
Event2013 Symposium on VLSI Technology, VLSIT 2013 - Kyoto, Japan
Duration: Jun 11 2013Jun 13 2013

Other

Other2013 Symposium on VLSI Technology, VLSIT 2013
CountryJapan
CityKyoto
Period6/11/136/13/13

Fingerprint

Demonstrations
Electrodes
Circuit simulation
Aspect ratio
Etching
RRAM

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Yu, S., Chen, H. Y., Deng, Y., Gao, B., Jiang, Z., Kang, J., & Wong, H. S. P. (2013). 3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation. In Digest of Technical Papers - Symposium on VLSI Technology [6576640]

3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation. / Yu, Shimeng; Chen, Hong Yu; Deng, Yexin; Gao, Bin; Jiang, Zizhen; Kang, Jinfeng; Wong, H. S Philip.

Digest of Technical Papers - Symposium on VLSI Technology. 2013. 6576640.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yu, S, Chen, HY, Deng, Y, Gao, B, Jiang, Z, Kang, J & Wong, HSP 2013, 3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation. in Digest of Technical Papers - Symposium on VLSI Technology., 6576640, 2013 Symposium on VLSI Technology, VLSIT 2013, Kyoto, Japan, 6/11/13.
Yu S, Chen HY, Deng Y, Gao B, Jiang Z, Kang J et al. 3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation. In Digest of Technical Papers - Symposium on VLSI Technology. 2013. 6576640
Yu, Shimeng ; Chen, Hong Yu ; Deng, Yexin ; Gao, Bin ; Jiang, Zizhen ; Kang, Jinfeng ; Wong, H. S Philip. / 3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation. Digest of Technical Papers - Symposium on VLSI Technology. 2013.
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