3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation

Shimeng Yu, Hong Yu Chen, Yexin Deng, Bin Gao, Zizhen Jiang, Jinfeng Kang, H. S.Philip Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

36 Scopus citations

Abstract

3D vertical RRAM scaling limit is investigated. 3D RRAM functionality along with a viable write/read scheme for the 3D array are experimentally demonstrated for the first time, using plane electrode with thickness (t m) down to 5 nm to minimize 3D stack height. Through 3D circuit simulation of the write/read margin, we conclude the practical lower bound for the lithographic half-pitch, F, is 26 nm for tm=5 nm and isolation SiO2 thickness of 6 nm, assuming a trench etching aspect ratio of 30. This is equivalent to 0.09F2/bit. Although a 2D array can scale further to F=13 nm, 3D array device density is 11× higher than a 2D array with the same number of bits (16kb). Shrinking tm is more effective for increasing integration density than shrinking F for a 3D array. To enlarge 3D array partition size, it is necessary to replace the commonly used TiN with lower resistivity electrode materials.

Original languageEnglish (US)
Title of host publication2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers
PagesT158-T159
StatePublished - Sep 9 2013
Event2013 Symposium on VLSI Technology, VLSIT 2013 - Kyoto, Japan
Duration: Jun 11 2013Jun 13 2013

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2013 Symposium on VLSI Technology, VLSIT 2013
CountryJapan
CityKyoto
Period6/11/136/13/13

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Yu, S., Chen, H. Y., Deng, Y., Gao, B., Jiang, Z., Kang, J., & Wong, H. S. P. (2013). 3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation. In 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers (pp. T158-T159). [6576640] (Digest of Technical Papers - Symposium on VLSI Technology).