### Abstract

3D vertical RRAM scaling limit is investigated. 3D RRAM functionality along with a viable write/read scheme for the 3D array are experimentally demonstrated for the first time, using plane electrode with thickness (t _{m}) down to 5 nm to minimize 3D stack height. Through 3D circuit simulation of the write/read margin, we conclude the practical lower bound for the lithographic half-pitch, F, is 26 nm for t_{m}=5 nm and isolation SiO_{2} thickness of 6 nm, assuming a trench etching aspect ratio of 30. This is equivalent to 0.09F^{2}/bit. Although a 2D array can scale further to F=13 nm, 3D array device density is 11× higher than a 2D array with the same number of bits (16kb). Shrinking t_{m} is more effective for increasing integration density than shrinking F for a 3D array. To enlarge 3D array partition size, it is necessary to replace the commonly used TiN with lower resistivity electrode materials.

Original language | English (US) |
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Title of host publication | Digest of Technical Papers - Symposium on VLSI Technology |

State | Published - 2013 |

Externally published | Yes |

Event | 2013 Symposium on VLSI Technology, VLSIT 2013 - Kyoto, Japan Duration: Jun 11 2013 → Jun 13 2013 |

### Other

Other | 2013 Symposium on VLSI Technology, VLSIT 2013 |
---|---|

Country | Japan |

City | Kyoto |

Period | 6/11/13 → 6/13/13 |

### Fingerprint

### ASJC Scopus subject areas

- Electrical and Electronic Engineering

### Cite this

*Digest of Technical Papers - Symposium on VLSI Technology*[6576640]

**3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation.** / Yu, Shimeng; Chen, Hong Yu; Deng, Yexin; Gao, Bin; Jiang, Zizhen; Kang, Jinfeng; Wong, H. S Philip.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Digest of Technical Papers - Symposium on VLSI Technology.*, 6576640, 2013 Symposium on VLSI Technology, VLSIT 2013, Kyoto, Japan, 6/11/13.

}

TY - GEN

T1 - 3D vertical RRAM - Scaling limit analysis and demonstration of 3D array operation

AU - Yu, Shimeng

AU - Chen, Hong Yu

AU - Deng, Yexin

AU - Gao, Bin

AU - Jiang, Zizhen

AU - Kang, Jinfeng

AU - Wong, H. S Philip

PY - 2013

Y1 - 2013

N2 - 3D vertical RRAM scaling limit is investigated. 3D RRAM functionality along with a viable write/read scheme for the 3D array are experimentally demonstrated for the first time, using plane electrode with thickness (t m) down to 5 nm to minimize 3D stack height. Through 3D circuit simulation of the write/read margin, we conclude the practical lower bound for the lithographic half-pitch, F, is 26 nm for tm=5 nm and isolation SiO2 thickness of 6 nm, assuming a trench etching aspect ratio of 30. This is equivalent to 0.09F2/bit. Although a 2D array can scale further to F=13 nm, 3D array device density is 11× higher than a 2D array with the same number of bits (16kb). Shrinking tm is more effective for increasing integration density than shrinking F for a 3D array. To enlarge 3D array partition size, it is necessary to replace the commonly used TiN with lower resistivity electrode materials.

AB - 3D vertical RRAM scaling limit is investigated. 3D RRAM functionality along with a viable write/read scheme for the 3D array are experimentally demonstrated for the first time, using plane electrode with thickness (t m) down to 5 nm to minimize 3D stack height. Through 3D circuit simulation of the write/read margin, we conclude the practical lower bound for the lithographic half-pitch, F, is 26 nm for tm=5 nm and isolation SiO2 thickness of 6 nm, assuming a trench etching aspect ratio of 30. This is equivalent to 0.09F2/bit. Although a 2D array can scale further to F=13 nm, 3D array device density is 11× higher than a 2D array with the same number of bits (16kb). Shrinking tm is more effective for increasing integration density than shrinking F for a 3D array. To enlarge 3D array partition size, it is necessary to replace the commonly used TiN with lower resistivity electrode materials.

UR - http://www.scopus.com/inward/record.url?scp=84883379890&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84883379890&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84883379890

SN - 9784863483477

BT - Digest of Technical Papers - Symposium on VLSI Technology

ER -