3D RRAM design and benchmark with 3d NAND FLASH

Pai Yu Chen, Cong Xu, Yuan Xie, Shimeng Yu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The monolithic 3D integration of resistive switching random access memory (RRAM) is one attractive approach to build high-density non-volatile memory. In this paper, the design considerations of 3D vertical RRAM architecture are presented from the device, circuit to system level. Due to the voltage drop and sneak path problem, the sub-array size of the 3D NAND is still limited as compared with that of the 3D NAND. To be cost-competitive with the 3D NAND, high on-state resistance, high I-V nonlinearity and low interconnect resistivity is required to enable Mb 3D RRAM sub-array. Although the 3D RRAM has disadvantage in array efficiency (consequently in cost per bit) than the 3D NAND, the 3D RRAM outperforms the 3D NAND in throughput performance at system-level.

Original languageEnglish (US)
Title of host publicationProceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479932962
DOIs
StatePublished - Jan 23 2014
Event2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 - Guilin, China
Duration: Oct 28 2014Oct 31 2014

Other

Other2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014
CountryChina
CityGuilin
Period10/28/1410/31/14

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Computer Science Applications

Cite this

Chen, P. Y., Xu, C., Xie, Y., & Yu, S. (2014). 3D RRAM design and benchmark with 3d NAND FLASH. In Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 [7021320] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICSICT.2014.7021320