3-D resistive memory arrays: From intrinsic switching behaviors to optimization guidelines

Haitong Li, Bin Gao, Hong Yu Henry Chen, Zhe Chen, Peng Huang, Rui Liu, Liang Zhao, Zizhen Jane Jiang, Lifeng Liu, Xiaoyan Liu, Shimeng Yu, Jinfeng Kang, Yoshi Nishi, H. S Philip Wong

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

3-D resistive switching random access memory (RRAM) is a promising candidate for high-density nonvolatile memory applications, as well as for monolithic 3-D integration interleaved with logic layers. In this paper, we develop a methodology for assessing and optimizing large-scale 3-D RRAM arrays. A systematic study on the intrinsic switching behaviors and optimization of 3-D RRAM arrays is performed, combining device measurements and 3-D array simulations. The dependence of programming voltage on array size, cell location and pulse parameters, statistical properties of operating 3-D RRAM arrays, and subthreshold disturbance on RRAM cells is experimentally investigated. Optimization guidelines for the performance and reliability of 3-D RRAM arrays from device level to architecture level are presented: 1) an optimized 1/n architecture for 100-kb 3-D RRAM arrays can improve write margin by 69.6% and reduce energy consumption by 75.6% compared with a conventional full-size array design; 2) a strategy of prioritizing storage location for reliable operation is presented; and 3) an optimal hopping barrier of oxygen ions is found to improve array immunity to disturbance.

Original languageEnglish (US)
Article number7225139
Pages (from-to)3160-3167
Number of pages8
JournalIEEE Transactions on Electron Devices
Volume62
Issue number10
DOIs
StatePublished - Oct 1 2015

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Data storage equipment
Energy utilization
Ions
Oxygen
Electric potential

Keywords

  • 3-D array
  • Optimization
  • Reliability
  • Resistive random access memory (RRAM)
  • Variability

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Li, H., Gao, B., Chen, H. Y. H., Chen, Z., Huang, P., Liu, R., ... Wong, H. S. P. (2015). 3-D resistive memory arrays: From intrinsic switching behaviors to optimization guidelines. IEEE Transactions on Electron Devices, 62(10), 3160-3167. [7225139]. https://doi.org/10.1109/TED.2015.2468602

3-D resistive memory arrays : From intrinsic switching behaviors to optimization guidelines. / Li, Haitong; Gao, Bin; Chen, Hong Yu Henry; Chen, Zhe; Huang, Peng; Liu, Rui; Zhao, Liang; Jiang, Zizhen Jane; Liu, Lifeng; Liu, Xiaoyan; Yu, Shimeng; Kang, Jinfeng; Nishi, Yoshi; Wong, H. S Philip.

In: IEEE Transactions on Electron Devices, Vol. 62, No. 10, 7225139, 01.10.2015, p. 3160-3167.

Research output: Contribution to journalArticle

Li, H, Gao, B, Chen, HYH, Chen, Z, Huang, P, Liu, R, Zhao, L, Jiang, ZJ, Liu, L, Liu, X, Yu, S, Kang, J, Nishi, Y & Wong, HSP 2015, '3-D resistive memory arrays: From intrinsic switching behaviors to optimization guidelines', IEEE Transactions on Electron Devices, vol. 62, no. 10, 7225139, pp. 3160-3167. https://doi.org/10.1109/TED.2015.2468602
Li, Haitong ; Gao, Bin ; Chen, Hong Yu Henry ; Chen, Zhe ; Huang, Peng ; Liu, Rui ; Zhao, Liang ; Jiang, Zizhen Jane ; Liu, Lifeng ; Liu, Xiaoyan ; Yu, Shimeng ; Kang, Jinfeng ; Nishi, Yoshi ; Wong, H. S Philip. / 3-D resistive memory arrays : From intrinsic switching behaviors to optimization guidelines. In: IEEE Transactions on Electron Devices. 2015 ; Vol. 62, No. 10. pp. 3160-3167.
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