Abstract
3-D resistive switching random access memory (RRAM) is a promising candidate for high-density nonvolatile memory applications, as well as for monolithic 3-D integration interleaved with logic layers. In this paper, we develop a methodology for assessing and optimizing large-scale 3-D RRAM arrays. A systematic study on the intrinsic switching behaviors and optimization of 3-D RRAM arrays is performed, combining device measurements and 3-D array simulations. The dependence of programming voltage on array size, cell location and pulse parameters, statistical properties of operating 3-D RRAM arrays, and subthreshold disturbance on RRAM cells is experimentally investigated. Optimization guidelines for the performance and reliability of 3-D RRAM arrays from device level to architecture level are presented: 1) an optimized 1/n architecture for 100-kb 3-D RRAM arrays can improve write margin by 69.6% and reduce energy consumption by 75.6% compared with a conventional full-size array design; 2) a strategy of prioritizing storage location for reliable operation is presented; and 3) an optimal hopping barrier of oxygen ions is found to improve array immunity to disturbance.
Original language | English (US) |
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Article number | 7225139 |
Pages (from-to) | 3160-3167 |
Number of pages | 8 |
Journal | IEEE Transactions on Electron Devices |
Volume | 62 |
Issue number | 10 |
DOIs | |
State | Published - Oct 1 2015 |
Keywords
- 3-D array
- Optimization
- Reliability
- Resistive random access memory (RRAM)
- Variability
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering