Abstract
This letter presents a compact output combining network for a packaged integrated asymmetric Doherty Power Amplifier (DPA). The combining network uses a new method for absorbing part of the peaking amplifier’s Cds into the impedance transformer, thus extending the C-L-C based “Cds absorption" technique to asymmetric DPAs. Based on the proposed combining network, a two-stage LDMOS integrated asymmetric DPA was designed and fabricated at 2.6 GHz. The fabricated IC is mounted in a quad flat no-lead (QFN) package. Under a single-tone continuous-wave (CW) signal at 2.6 GHz, the DPA achieves peak power of 46 dBm, linear gain of 31.7 dB and 48% power-added efficiency (PAE) at 8 dB output power back-off (OBO). The DPA also demonstrates good linearizability by meeting the 5G spectrum mask and achieving a DPD corrected ACPR better than -51dBc for 160 MHz long term evolution (LTE).
Original language | English (US) |
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Journal | IEEE Microwave and Wireless Components Letters |
DOIs | |
State | Accepted/In press - 2021 |
Keywords
- Doherty Power Amplifier (DPA)
- Gain
- Impedance
- Inverters
- LDMOS
- Logic gates
- Long Term Evolution
- Optimized production technology
- Power generation
- RFIC
- integrated Doherty
- long term evolution (LTE)
ASJC Scopus subject areas
- Condensed Matter Physics
- Electrical and Electronic Engineering