1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays

Amr M.S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

RRAM-based memories provide non-volatile and scalable data storage in advanced technologies. RRAM device, as a non-charge-based device, is intrinsically immune to radiation effects which promotes its usage in applications subject to high radiations such as space, aircraft, and medical devices. Yet, the half-select cells in the 1T1R array suffer from multiple- and single-events upset resulting from the collection of charged heavy-ions on the junction of the MOS access device of the memory cell. In this paper, we propose a novel methodology for detecting and correcting single-event upset in 1T1R RRAM memory array by adding an extra biased RRAM device. Our simulation results on 8Gb HfOx RRAM arrays demonstrate that the proposed technique can detect and fix the soft errors induced by the heavy-ion strikes with a minor increase in the energy consumption of the read and write operations of 0.2% and 0.1%, respectively.

Original languageEnglish (US)
Title of host publicationProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
PublisherIEEE Computer Society
Pages12-15
Number of pages4
Volume2017-October
ISBN (Electronic)9781509066247
DOIs
StatePublished - Jan 8 2018
Event12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
Duration: Oct 25 2017Oct 28 2017

Other

Other12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
CountryChina
CityGuiyang
Period10/25/1710/28/17

Fingerprint

Data storage equipment
Heavy ions
Radiation effects
Energy utilization
Aircraft
RRAM
Radiation

Keywords

  • Heavy-ions
  • Non-volatile memory
  • RRAM 1T1R array
  • Single-event upset
  • Soft errors

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Tosson, A. M. S., Yu, S., Anis, M. H., & Wei, L. (2018). 1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays. In Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (Vol. 2017-October, pp. 12-15). IEEE Computer Society. https://doi.org/10.1109/ASICON.2017.8252399

1T2R : A novel memory cell design to resolve single-event upset in RRAM arrays. / Tosson, Amr M.S.; Yu, Shimeng; Anis, Mohab H.; Wei, Lan.

Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Vol. 2017-October IEEE Computer Society, 2018. p. 12-15.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Tosson, AMS, Yu, S, Anis, MH & Wei, L 2018, 1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays. in Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. vol. 2017-October, IEEE Computer Society, pp. 12-15, 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017, Guiyang, China, 10/25/17. https://doi.org/10.1109/ASICON.2017.8252399
Tosson AMS, Yu S, Anis MH, Wei L. 1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays. In Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Vol. 2017-October. IEEE Computer Society. 2018. p. 12-15 https://doi.org/10.1109/ASICON.2017.8252399
Tosson, Amr M.S. ; Yu, Shimeng ; Anis, Mohab H. ; Wei, Lan. / 1T2R : A novel memory cell design to resolve single-event upset in RRAM arrays. Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Vol. 2017-October IEEE Computer Society, 2018. pp. 12-15
@inproceedings{31b262d8478340039cb4b8b94d749833,
title = "1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays",
abstract = "RRAM-based memories provide non-volatile and scalable data storage in advanced technologies. RRAM device, as a non-charge-based device, is intrinsically immune to radiation effects which promotes its usage in applications subject to high radiations such as space, aircraft, and medical devices. Yet, the half-select cells in the 1T1R array suffer from multiple- and single-events upset resulting from the collection of charged heavy-ions on the junction of the MOS access device of the memory cell. In this paper, we propose a novel methodology for detecting and correcting single-event upset in 1T1R RRAM memory array by adding an extra biased RRAM device. Our simulation results on 8Gb HfOx RRAM arrays demonstrate that the proposed technique can detect and fix the soft errors induced by the heavy-ion strikes with a minor increase in the energy consumption of the read and write operations of 0.2{\%} and 0.1{\%}, respectively.",
keywords = "Heavy-ions, Non-volatile memory, RRAM 1T1R array, Single-event upset, Soft errors",
author = "Tosson, {Amr M.S.} and Shimeng Yu and Anis, {Mohab H.} and Lan Wei",
year = "2018",
month = "1",
day = "8",
doi = "10.1109/ASICON.2017.8252399",
language = "English (US)",
volume = "2017-October",
pages = "12--15",
booktitle = "Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017",
publisher = "IEEE Computer Society",

}

TY - GEN

T1 - 1T2R

T2 - A novel memory cell design to resolve single-event upset in RRAM arrays

AU - Tosson, Amr M.S.

AU - Yu, Shimeng

AU - Anis, Mohab H.

AU - Wei, Lan

PY - 2018/1/8

Y1 - 2018/1/8

N2 - RRAM-based memories provide non-volatile and scalable data storage in advanced technologies. RRAM device, as a non-charge-based device, is intrinsically immune to radiation effects which promotes its usage in applications subject to high radiations such as space, aircraft, and medical devices. Yet, the half-select cells in the 1T1R array suffer from multiple- and single-events upset resulting from the collection of charged heavy-ions on the junction of the MOS access device of the memory cell. In this paper, we propose a novel methodology for detecting and correcting single-event upset in 1T1R RRAM memory array by adding an extra biased RRAM device. Our simulation results on 8Gb HfOx RRAM arrays demonstrate that the proposed technique can detect and fix the soft errors induced by the heavy-ion strikes with a minor increase in the energy consumption of the read and write operations of 0.2% and 0.1%, respectively.

AB - RRAM-based memories provide non-volatile and scalable data storage in advanced technologies. RRAM device, as a non-charge-based device, is intrinsically immune to radiation effects which promotes its usage in applications subject to high radiations such as space, aircraft, and medical devices. Yet, the half-select cells in the 1T1R array suffer from multiple- and single-events upset resulting from the collection of charged heavy-ions on the junction of the MOS access device of the memory cell. In this paper, we propose a novel methodology for detecting and correcting single-event upset in 1T1R RRAM memory array by adding an extra biased RRAM device. Our simulation results on 8Gb HfOx RRAM arrays demonstrate that the proposed technique can detect and fix the soft errors induced by the heavy-ion strikes with a minor increase in the energy consumption of the read and write operations of 0.2% and 0.1%, respectively.

KW - Heavy-ions

KW - Non-volatile memory

KW - RRAM 1T1R array

KW - Single-event upset

KW - Soft errors

UR - http://www.scopus.com/inward/record.url?scp=85044711711&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85044711711&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2017.8252399

DO - 10.1109/ASICON.2017.8252399

M3 - Conference contribution

AN - SCOPUS:85044711711

VL - 2017-October

SP - 12

EP - 15

BT - Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017

PB - IEEE Computer Society

ER -