Abstract
Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intradie and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation-two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO2 interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO2 interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 128-134 |
| Number of pages | 7 |
| Journal | Journal of Computational Electronics |
| Volume | 9 |
| Issue number | 3-4 |
| DOIs | |
| State | Published - Dec 2010 |
Fingerprint
Keywords
- Monte Carlo device simulations
- Random dopant fluctuations
- Random telegraph noise fluctuations
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Atomic and Molecular Physics, and Optics
- Electronic, Optical and Magnetic Materials
- Modeling and Simulation
Cite this
1/f noise : Threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps. / Ashraf, Nabil; Vasileska, Dragica.
In: Journal of Computational Electronics, Vol. 9, No. 3-4, 12.2010, p. 128-134.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - 1/f noise
T2 - Threshold voltage and ON-current fluctuations in 45 nm device technology due to charged random traps
AU - Ashraf, Nabil
AU - Vasileska, Dragica
PY - 2010/12
Y1 - 2010/12
N2 - Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intradie and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation-two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO2 interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO2 interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.
AB - Discrete impurity effects in terms of their statistical variations in number and position in the inversion and depletion region of a MOSFET, as the gate length is aggressively scaled, have recently been investigated as being a major cause of reliability degradation observed in intradie and die-to-die threshold voltage variation on the same chip resulting in significant variation in saturation drive (on) current and transconductance degradation-two key metrics for benchmark performance of digital and analog integrated circuits. In this paper, in addition to random dopant fluctuations (RDF), the influence of random number and position of interface traps lying close to Si/SiO2 interface has been examined as it poses additional concerns because it leads to enhanced experimentally observed fluctuations in drain current and threshold voltage. In this context, the authors of this article present novel EMC based simulation study on trap induced random telegraph noise (RTN) responsible for statistical fluctuation pattern observed in threshold voltage, its standard deviation and drive current in saturation for 45 nm gate length technology node MOSFET device. From the observed simulation results and their analysis, it can be projected that with continued scaling in gate length and width, RTN effect will eventually supersede as a major reliability bottleneck over the already present RDF phenomenon. The fluctuation patterns observed by EMC simulation outcomes for both drain current and threshold voltage have been analyzed for the cases of single trap and two traps closely adjacent to one another lying in the proximity of the Si/SiO2 interface between source to drain region of the MOSFET and explained from analytical device physics perspectives.
KW - Monte Carlo device simulations
KW - Random dopant fluctuations
KW - Random telegraph noise fluctuations
UR - http://www.scopus.com/inward/record.url?scp=78649848108&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78649848108&partnerID=8YFLogxK
U2 - 10.1007/s10825-010-0330-y
DO - 10.1007/s10825-010-0330-y
M3 - Article
AN - SCOPUS:78649848108
VL - 9
SP - 128
EP - 134
JO - Journal of Computational Electronics
JF - Journal of Computational Electronics
SN - 1569-8025
IS - 3-4
ER -