τAU: Timing Analysis under Uncertainty

Sarvesh Bhardwaj, Sarma B K Vrudhula, David Blaauw

Research output: Chapter in Book/Report/Conference proceedingConference contribution

43 Scopus citations

Abstract

Due to excessive reduction in the gate length, dopant concentrations and the oxide thickness, even the slightest of variations in these quantities can result in significant variations in the performance of a device. This has resulted in a need for efficient and accurate techniques for performing Statistical Analysis of circuits. In this paper 1 we propose a methodology based on Bayesian Networks for computing the exact probability distribution of the delay of a circuit. In case of large circuits where it is not possible to compute the exact distribution, we propose methods to reduce the problem size and get a tight lower bound on the exact distribution.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Pages615-620
Number of pages6
StatePublished - 2003
Externally publishedYes
EventIEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers - San Jose, CA, United States
Duration: Nov 9 2003Nov 13 2003

Other

OtherIEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers
CountryUnited States
CitySan Jose, CA
Period11/9/0311/13/03

ASJC Scopus subject areas

  • Software

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  • Cite this

    Bhardwaj, S., Vrudhula, S. B. K., & Blaauw, D. (2003). τAU: Timing Analysis under Uncertainty. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (pp. 615-620)