τAU: Timing Analysis under Uncertainty

Sarvesh Bhardwaj; Sarma B K Vrudhula; David Blaauw

τAU: Timing Analysis under Uncertainty

Sarvesh Bhardwaj, Sarma B K Vrudhula, David Blaauw

Computing and Augmented Intelligence, School of (IAFSE-SCAI)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

47 Scopus citations

Abstract

Due to excessive reduction in the gate length, dopant concentrations and the oxide thickness, even the slightest of variations in these quantities can result in significant variations in the performance of a device. This has resulted in a need for efficient and accurate techniques for performing Statistical Analysis of circuits. In this paper ¹ we propose a methodology based on Bayesian Networks for computing the exact probability distribution of the delay of a circuit. In case of large circuits where it is not possible to compute the exact distribution, we propose methods to reduce the problem size and get a tight lower bound on the exact distribution.

Original language	English (US)
Title of host publication	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Pages	615-620
Number of pages	6
State	Published - 2003
Event	IEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers - San Jose, CA, United States Duration: Nov 9 2003 → Nov 13 2003

Other

Other	IEEE/ACM International Conference on Computer Aided Design ICCAD 2003: IEEE/ACM Digest of Technical Papers
Country/Territory	United States
City	San Jose, CA
Period	11/9/03 → 11/13/03

ASJC Scopus subject areas

Software

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title = "τAU: Timing Analysis under Uncertainty",

abstract = "Due to excessive reduction in the gate length, dopant concentrations and the oxide thickness, even the slightest of variations in these quantities can result in significant variations in the performance of a device. This has resulted in a need for efficient and accurate techniques for performing Statistical Analysis of circuits. In this paper 1 we propose a methodology based on Bayesian Networks for computing the exact probability distribution of the delay of a circuit. In case of large circuits where it is not possible to compute the exact distribution, we propose methods to reduce the problem size and get a tight lower bound on the exact distribution. ",

author = "Sarvesh Bhardwaj and Vrudhula, {Sarma B K} and David Blaauw",

year = "2003",

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pages = "615--620",

booktitle = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers",

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AU - Vrudhula, Sarma B K

AU - Blaauw, David

PY - 2003

Y1 - 2003

N2 - Due to excessive reduction in the gate length, dopant concentrations and the oxide thickness, even the slightest of variations in these quantities can result in significant variations in the performance of a device. This has resulted in a need for efficient and accurate techniques for performing Statistical Analysis of circuits. In this paper 1 we propose a methodology based on Bayesian Networks for computing the exact probability distribution of the delay of a circuit. In case of large circuits where it is not possible to compute the exact distribution, we propose methods to reduce the problem size and get a tight lower bound on the exact distribution.

AB - Due to excessive reduction in the gate length, dopant concentrations and the oxide thickness, even the slightest of variations in these quantities can result in significant variations in the performance of a device. This has resulted in a need for efficient and accurate techniques for performing Statistical Analysis of circuits. In this paper 1 we propose a methodology based on Bayesian Networks for computing the exact probability distribution of the delay of a circuit. In case of large circuits where it is not possible to compute the exact distribution, we propose methods to reduce the problem size and get a tight lower bound on the exact distribution.

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M3 - Conference contribution

AN - SCOPUS:0347409182

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BT - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Y2 - 9 November 2003 through 13 November 2003

ER -

τAU: Timing Analysis under Uncertainty

Abstract

Other

ASJC Scopus subject areas

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