Employ and calibrate reliability models developed in Phase I of IRIS-TERCI to CMOS process of interest for Phase II of IRIS-TERCI (IBM technologies ranging from 90 nm to 45 nm). Correlate these models with fundamental reliability physics in scaled CMOS technology, including their statistical behavior. Integrate the newly developed reliability models into circuit performance analysis flow developed in Phase I of IRIS-TERCI. Develop large-scale simulation algorithms to efficiently predict statistical reliability effects on GFE TA chips, under process variability and dynamic circuit operations. Identify critical stress conditions, degradation signatures and stimuli for digital and analog designs. Predict IC failure rate for various design units from process and operation parameters. Evaluate& fine tune the model predictions with silicon experimental data. Assess the priority of various failure mechanisms through model development and silicon experimental data. Implement calibrated reliability models and the MTTF simulation methodology to multiple commercial tool platforms. Transfer these models& techniques to other teams in IRIS-TERCI and the Government.
|Effective start/end date||2/20/13 → 8/19/14|
- DOD: Defense Advanced Research Projects Agency (DARPA): $120,000.00