Structural Fault Modeling, Testing, and Defect Level Estimation for Analog/RF Circuits

Project: Research project

Project Details

Description

Structural Fault Modeling, Testing, and Defect Level Estimation for Analog/RF Circuits Structural Fault Modeling, Testing, and Defect Level Estimation for Analog/RF Circuits This project aims at bringing a new vision to the fault-based testing domain for analog/RF circuits. Our aim is to revisit the definition of what constitutes a fault, particularly for parametric faults, and develop test evaluation tools and the associated defect level estimation tools that are useful in a practical industry environment. These tools will be applicable to a wide range of test development efforts by other researchers and will provide a mechanism for industry collaborators to select the best test solution that fits their designs.
StatusFinished
Effective start/end date8/1/087/31/09

Funding

  • SRCCO Inc.: $85,000.00

Fingerprint

Explore the research topics touched on by this project. These labels are generated based on the underlying awards/grants. Together they form a unique fingerprint.