Structural Fault Modeling, Testing, and Defect Level Estimation for Analog/RF Circuits - Year 2 Structural Fault Modeling, Testing, and Defect Level Estimation for Analog/RF Circuits This project aims at bringing a new vision to the fault-based testing domain for analog/RF circuits. Our aim is to revisit the definition of what constitutes a fault, particularly for parametric faults, and develop test evaluation tools and the associated defect level estimation tools that are useful in a practical industry environment. These tools will be applicable to a wide range of test development efforts by other researchers and will provide a mechanism for industry collaborators to select the best test solution that fits their designs.
|Effective start/end date||8/1/09 → 4/30/11|
- SRCCO Inc.: $90,000.00
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