As semiconductor technology scales into the 22nm node and below, robust design of memory cells to function correctly under all process, voltage, and temperature conditions remains as a tremendous challenge. This proposal pursues innovative methodologies that will enable fast sign-off of on-chip memory at the end of the silicon roadmap and beyond, through the seamless integration of physical modeling of variations, fast statistical analysis for extreme tails of performance variability, robust optimization strategies, and efficient characterization techniques. Broader impacts: This research effort will facilitate fundamental research on reliable design with unreliable components, enhance design productivity for a wide range of applications, and expedite statistical design solution for emerging nanoelectronic devices. In addition, through novel education curricula and web-based dissemination tools, this project will transfer the newly developed design knowledge to a diverse population of students, who will lead the creation of future nanoscale integrated systems of all types, from computation, communication, to consumer electronics. Motivation: The scaling of on-chip memory is tremendously challenged by the excessive amount of process variations and reliability degradation at the 22nm node and below. In practice, full custom design and extensive experimentation on test silicon are often necessary to achieve the desired bit density, cell stability, speed, power, and yield. Although such an expensive approach is acceptable in todays chip design, it drastically reduces design productivity and predictability. The situation becomes even more severe when the ever-increasing nature of variations narrows the design window and exacerbates memory design complexity. In this context, it is essential to develop an innovative sign-off methodology that is capable to create memory cells with sufficient accuracy, efficiency, and flexibility to technology choice, circuit topology and design needs. Presently, research and education programs are devoid of such a methodology addressing the demands of robust memory design towards the 10nm node. Intellectual merit: This proposal will develop a set of compact models and statistical CAD tools for fast memory synthesis. This suite will comprise predictive variability models, statistical sampling schemes, robust optimization algorithms, and in-situ characterization techniques to improve the predictability and productivity of future memory design. The cornerstone will be new physical models to predict transistor variability and reliability from process, device and design choices. Their accuracy will be validated by first-principle simulations and silicon characterization. Built upon these transistor-level models, statistical circuit analysis methodologies will be developed for fast memory synthesis over an extremely large range of variations. Through joint efforts between device modeling and statistical simulation, a novel Markovchain- based technique will be specialized for the analysis and optimization of on-chip memory. Furthermore, these new outcomes will be integrated into an online framework to statistically benchmark post-Si memory design. This open environment will perform initial assessment of promising devices, helping illustrate the diverse opportunities of memory design beyond the 10nm node. Education: The principal goal of the education component is to teach students key concepts of process variability and statistical methods in nanoscale circuit design both early and often, and transfer a diverse population of students to industry and academia with relevant design knowledge. To accomplish this goal, we will focus on: (1) education of K-12 teachers to promote early conceptual understanding of engineering, with outreach efforts to female and minority students; (2) the revision of undergraduate-level courses and the development of new graduate-level courses
|Effective start/end date||8/15/10 → 7/31/13|
- National Science Foundation (NSF): $224,874.00
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