Self-Healing Self-Adaptive Low Power High-Resolution Analog-to-Digital Converters for Space Applications

Project: Research project

Project Details

Description

This research is in the continuation of the ongoing project with JPL on designing high resolution low power analog to digital converters to work in the extreme lunar environment. The analog circuit should work reliably and without degradation in performance over the wide temperature range of -230 to +120 C. In order to achieve this goal, we have proposed a radiation tolerant self healing self adaptive data converter. Healing and adaptivity features of the converter is embedded in each of its major blocks through use a combination of analog and digital calibration techniques that continuously monitor the operation of each block and ensure their reliable performance over these extreme temperature specifications. In addition to local calibration routines, global calibration approaches are also used to guarantee that the data converter is capable of working with targeted resolution in the whole temperature range of -230 to +120 C. To ensure successful design and simulation of the novel circuit, this project is empowered by the accurate compact models for CMOS. Novel CMOS compact models for low temperatures are being developed as part of the current project by the PSP model group at ASU. Accomplishments and targeted deliverables for the first year of this project (FY 08) are: -Parameter extraction of bulk CMOS under radiation and extreme temperature range (in progress) -Developing the compact models for bulk CMOS transistors across extreme temperature ranges (in progress) -System design of a low power high resolution sigma delta modulator for extreme temperature (completed) -Design of self-healing tunable building blocks of a sigma delta modulator (completed) -Tape out of the major building blocks (March 2008) -Test and verifications of the major building block (April 2008) -Design of a prototype high resolution sigma delta modulator uses the proposed tuning techniques (May 2008) In summary, the design of tunable blocks necessary for the high resolution data converter will be completed successfully in the first year of the project. Accurate compact models for low temperature operation of CMOS have been also developed. In the second year of this project, we intend to follow on the accomplishments of the first year. This is done by delivering a prototype high resolution sigma delta converter that integrates the tunable blocks designed in the FY08. The developed compact models for extreme temperature will be exploited in this design cycle. For FY09 we intend to increase the resolution of data converter from the initial target of 20 Bits to 24 Bits which makes this data converter an excellent choice for high precision instrumentation. In order to achieve this high resolution over the extended temperature range, we propose additional novel techniques such as using CHS (Correlation Double Sampling) for the front end integrator to reduce low frequency noise of this stage and also using a power-noise optimization method in architecture and system level design of the sigma delta modulator asexplained in section 9. The major milestones for FY 2009 are: - Characterize the building blocks that were fabricated in FY 08 - Incorporate the developed CMOS compact models in the design of sigma delta modulator - Modeling TID effects with radiation-enabled compact transistors over temperature -Tape out of an extremely high resolution (24-Bit) ADC with calibrated cryo compact models -Test and verification of the ADC across temperature and TID The projected deliverables for FY 2009 are: - Extremely high resolution (24-Bit) sigma delta analog to digital converter -The complete compact model for bulk CMOS for extreme temperature
StatusFinished
Effective start/end date4/2/093/9/10

Funding

  • National Aeronautics Space Administration (NASA): $80,000.00

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