Security Assurance in a Shared Hardware Architecture

Project: Research project

Project Details


Security Assurance in a Shared Hardware Architecture Security Assurance in a Shared Hardware Architecture Executive Summary The current model of separate instantiations of HPC clusters when working with classified information imposes a significant burden that is reflected in the final of products. The total utilization activity on a given HPC cluster is a small percentage of the available computer cycles. Consolidating the computing environment into a leveraged Separately Accredited Network service will reduce the amount of hardware purchased and the number of support personnel required. Research conducted in 2011 identified a mechanism for coordinating access to networked resources from mutually untrusted HPC applications that share a multiprocessor computing platform. This access includes capabilities to receive, as well as send information over a network among entities of a trusted group, deny access to non-trusted members, and/or to control access to network storage through the issuance of a temporary locking mechanism. This project would develop an operational prototype that can be tested against a real environment. The goal will be to deliver the prototype for testing by new Raytheon CODE Center with the aim of seeking government sponsorship to allow concurrent access to HPC hardware. The research and final product will be developed jointly between Raytheon personnel and the IMPACT Lab at ASU, Tempe. The initial project in 2011 resulted in the filing of an Intellectual Property Disclosure with the intention of filing a Patent Application.
Effective start/end date6/1/121/31/13


  • INDUSTRY: Domestic Company: $60,000.00


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