Low-Power Rad-Hard ADC Design for Detector Environments Low-Power Rad-Hard ADC Design for Detector Environments The is tasked, through a Phase I SBIR with D.O.E, to design a programmable 12/14 bit, 40/100 Ms/s ADC using IBM's 130nm SiGe BiCMOS 8HP process. ASU is proposing to support this effort from September, 2008 to February, 2009: Optimization ofthe proposed architecture: 5-5-5-2 pipe lined flash. Radiation hardening advice for Sample and Hold circuits. Radiation threat considerations Radiation hardening considerations for an MDAC, flash quantizer and error correction circuits.
|Effective start/end date||10/1/08 → 3/31/09|
- US Department of Energy (DOE): $5,642.00
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