IUCRC FRP: Collaborative Research: Testability and timing analysis in nanoscale designs in the presence of process variations

Project: Research project

Project Details


PROJECT SUMMARY Overview: Embedded systems are widely used in various applications, and improve virtually every aspect of human life and the society. A significant challenge is to develop high-performance, reliable, low cost, and lowpower integrated circuits which are core components in every modern embedded system. This project tackles this challenge by developing testability and timing analysis techniques for integrated circuits. For over thirty years, static CMOS logic has been the dominant design methodology for digital systems. During this period dimensions of devices were scaled down from 10,000nm to 22nm (a 500X reduction), density increased by 65,000X, and the technology transitioned through 18 process generations. As CMOS technology is scaled down in to the deep nanometer regime, control of the physical parameters, such as the feature size of transistors, their doping levels, and oxide thicknesses, has become extremely difficult. These and other factors are contributing to significant loss of yield of the manufactured circuits and are threatening the growth and profitability of the semiconductor industry. Test and design methodologies must be variation-aware.
Effective start/end date9/15/148/31/17


  • National Science Foundation (NSF): $100,000.00


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