Embedded systems, which have been widely used in various applications, will be rapidly evolved into many forms and ubiquitously deployed to improve virtually every aspect of human life and the society. A significant challenge in the path to this bright future is to develop highperformance and low-power System-on-a-Chip (SoC) devices, which are core components in every modern embedded system. This project tackles this challenge by developing both synthesis and circuit techniques that enable using Threshold Logic (TL) circuits to implement complex SoCs for high-performance and low-power embedded systems. Recent research has demonstrated that TL circuits outperform conventional logic circuits for CMOS technologies and can serve as an excellent choice for implementing digital circuits using future nano devices. The proposed research develops effective TL circuit synthesis algorithms that simultaneously optimize power, area, speed, and robustness of the TL circuits. It develops analytical models and subsequently establishes systematic design and optimization procedures for TL gate design using both CMOS and future nano devices. It also explores new techniques to achieve post-fabrication configuration at the TL gate level to effectively cope with process variations and defects, which are expected to be worsen for future atomic-scale devices. Furthermore, the project investigates applying the developed TL circuit techniques in Time-to- Digital Converter (TDC) based Analog-to-Digital Converter (ADC) designs. Finally, the developed techniques will be evaluated using the benchmark circuits provided or suggested by member companies of the NSF IUCRC Center for Embedded Systems which have interests and expertise in embedded systems for a wide range of applications. Intellectual Merit: Despite their excellent potentials to outperform conventional logic circuits, TL circuits have not yet been adopted by semiconductor industries to address the low-power and high-performance challenges in the development of embedded systems. This is mainly due to the lack of effective TL synthesis tools, systematic TL gate design and optimization procedures, and the concerns of circuit robustness. The project takes a unified approach to simultaneously address these difficult challenges. The research will help pave the way for a new paradigm for implementing high-performance low-power SoCs, which significantly benefits embedded systems in various aspects. The merits of the proposed approaches include new synthesis algorithms to accommodate large TL functions and to cope with process variations, integrating accurate analytical TL gate models in synthesis procedures, and coping with process variations by exploring post-fabrication configuration at the TL gate level. In addition, the proposed work will extend TL circuit techniques to the domain of mixed-signal circuit design. Broader Impact: The proposed research activities will eventually help semiconductor companies produce more reliable and affordable microprocessors and SoC chips, which directly promote the development of more sophisticated, power-efficient and miniature embedded systems. This will clearly enrich various aspects of human life and benefit many industries. The proposed research on implementing TL circuits using future nano devices will help the development of future embedded systems that have great complexity beyond todays imagination. In addition, the project will be used as a vehicle to help students develop interests and abilities to conduct research in post-CMOS technologies. It will also provide research opportunities to undergraduate students. Such experiences will likely inspire their interests in technology and motivate them for graduate studies. Both institutions have an excellent tradition in recruiting and graduating students from underrepresented groups. Therefore, the project will also positively impact the diversity of future workforce.
|Effective start/end date||8/1/12 → 7/31/15|
- National Science Foundation (NSF): $100,000.00