Project Summary KeyWords: compiler, multi-core processors, power-efficiency As we scale technology nodes for power-efficiency and performance, we are destined to arrive at the power-wall (an upper limit on acceptable power consumption for a performance gradient), and therefore industry designers have shifted gears towards developing multi-core and many core solutions for their computation needs. As the number of cores scale, scaling the memory architecture is a major challenge. Scratch-pad memory based multi-core architectures (e.g., in the IBM Cell multi-core processor) are the most promising technology that will sustain our current technological growth rate. However, the availability and usability of such processors (with 10X more power-efficiency), in the market is curtailed by the lack of a generic compiler that increased software development cost. We have developed the first compiler technology that will enable such multi-core processors without memory management in hardware, to execute traditional and modern applications.
|Effective start/end date||7/1/13 → 6/30/14|
- National Science Foundation (NSF): $50,000.00
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