EAGER: Low-Power VLSI Applications of Neuromorphic Circuit Construction with Nanoelectronic Devices EAGER: Low-Power VLSI Applications of Neuromorphic Circuit Construction with Nanoelectronic Devices One of the fundamental problems in the continual scaling of transistors is reduced analog and mixed signal performance such as subthreshold slope and degraded switching performance. Several new nano-devices are being developed and investigated as an alternative to ultra deep submicron CMOS, such as transistors based on the field-effect control of impact-ionization (IMOS) , and feedback FETs . Several of steep subthreshold-slope transistors may be very beneficial for nonlinear neuromorphic computing systems. In recent years, several artificial brain projects have been launched that rely on computer simulations of neural behavior on multiprocessors. These simulations are large and slow, with simulations running well behind real time even for small brain functions. Neuromorhic computing platforms learn to compute a function using example inputs and outputs that are spatially and temporally correlated. In this early-concept exploratory research project, fundamental building blocks of neural computing, such as perceptron and analog memory, will be mapped to emerging nanoscale devices that are compatible with CMOS design infrastructure. With this seed funding, as an ultra-low-power VLSI application vehicle, we will build a short latency dynamic Neuromorphic Branch Predictors (NBP) suitable for an instruction level parallel microarchitecture, demonstrating the potential of constructive neuromorphic design with nanoelectronic devices. This platform would enable future microarchitectural improvements on microprocessors and digital signal processors, analog and mixed signal performance enhancers, on-chip signaling, power, energy management systems and sensor signal processing.
|Effective start/end date||9/1/09 → 8/31/11|
- NSF-ENG-ECCS: Division of Electrical Communications Systems (ECS): $54,539.00
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