Power dissipation is widely recognized as the key bottleneck in electronic design and the development of energy efficient solutions is critical to the survival of the semiconductor industry. Moorefs law, through new technologies such as FinFET devices and 3D integration, promises to consistently deliver increasing transistor densities. However, starting around the 65nm node, device scaling no longer delivers the energy gains that drove the semiconductor growth of the past several decades. The supply voltage has remained essentially constant since then and energy efficiency has stagnated. These factors have created a design paradox: more gates can now fit on a die, but cannot actually be used due to strict power limits. Alternatives to CMOS technology, such as nano-devices, show little indication of becoming viable in the next decade and none has gained sufficient traction to overthrow the multibillion dollar investments in the current semiconductor infrastructure. Hence, solutions to the power conundrum must come from within CMOS technology through enhanced architectures, circuits, and devices. Intellectual merit: In our view, the solution to this energy crisis is the universal application of aggressive low voltage operation across all computation platforms. We target gnear-threshold computingh (NTC), where devices operate at or near their threshold voltage to obtain 10X or higher energy efficiency improvements. The use of ultra-low voltage operation, and in particular subthreshold operation (Vdd < Vth), was first proposed over 30 years ago. However, the challenges that arise from operating in this regime have relegated subthreshold operation to a handful of niche markets. Given the current energy crisis and stagnated voltage scaling we foresee the need for a radical paradigm shift where ultra-low voltage operation is applied ubiquitously across application platforms. We intend to accomplish this with a two-fold approach: First, instead of subthreshold operation, we target near-threshold operation where ~10X energy gains are achieved with a challenging, but manageable, performance loss of ~10X. Compared to traditional subthreshold operation, which realizes a 20X energy gain for 100-500X performance loss, NTC provides a much more favorable tradeoff. Second, we focus on three key challenges that to date have kept low voltage operation from widespread use: 1) 10X loss in performance, 2) 5X increase in performance variation, and 3) 5 orders of magnitude increase in functional failure of memory and increased logic failures. Overcoming these barriers is the challenge we address in this work. To this end, we present a synergistic approach combining methods from algorithm and architecture levels to the circuit and technology levels, as detailed in this report. Further, to enable the successful application of NTC across the performance spectrum, we examine different application areas and propose domain-specific solutions in each. Sensor-based platforms critically depend on ultra-low power (.W) and reduced form factor (mm3) to unlock new applications, such as medically implanted monitors. In this space we propose ultra-low power communication protocols and ultra-low standby power approaches that take advantage of the low duty cycle of these applications. Personal computing platforms, are becoming increasingly wireless and miniaturized and are severely limited by tradeoffs between battery lifetimes and performance. In this space we focus on the requirement for NTC to dynamically respond to widely varying performance requirements. Finally, high-performance platforms in large data centers dissipate so much power that these centers are often co-located near cheap energy sources and dedicated cooling facilities with large carbon footprints. In this application domain, we address the need for efficient and high bandwidth access of mass storage devices. Finally, to demonstrate the feasibility of our
|Effective start/end date||8/1/09 → 7/31/14|
- NSF-ENG-ECCS: Division of Electrical Communications Systems (ECS): $705,507.00
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