Connection One - Communications Circuits and Systems Research Center

Connection One - Communications Circuits and Systems Research Center CONNECTION ONE - COMMUNICATIONS CIRCUITS AND SYSTEMS RESEARCH CENTER INDUSTRY PERCEPTIONS OF I/URCRC PROGRAMMATIC OUTCOMES NSF - U of A Supplement NSF - REU Supplement CDADIC and Connection One TIE Project Connection One Connection One - Communications Circuits and Systems Research Center REU Supplement: Connection One - Communications and Systems Research Center Supplemental Funding to IUCRC: 2007 Compendium of Technology Breakthroughs Connection One - Communications Circuits and Systems Research Center Parallel Co-Design Methodology for Electronic Systems-on-a-Chip (supplement to C1) EDA (electronics design automation)-based tools are already playing an increasingly central role in designing digital chips and their surrounding connectivity. Such toolsets have also provided confidence to developing virtual prototypes to significantly reduce costs and design-to-market cycle. The overwhelming push to move to smaller process geometries and higher performing chips with higher levels of functionality is generating a need for new architectures in 3D packaging with stacked dies, 3D transistors, and Systems-on-Chip (SoC). These design trends point to a trend for concurrent IC package and chip design. That is, chip designers are being asked to incorporate package-aware optimization and tradeoff software into their plan and to test how a signal propagates/radiates through the die, package, housing substrate and the PCBs. High speed chip designer are therefore faced with a great need for integrated design methodologies that allow for full-chip integration early in the design. Herewith, we propose a co-design platform based on new domain decomposition (DD) concepts. Namely, each circuit or volume domain will adapt different simulation software for accurate and efficient modeling of complex RF-digital chip package. These individual simulation tools, including the finite element frequency and time domain methods, SPICE-like circuit tools, EMC/EMI specific design tools etc, will then be integrated and iterated through a robust transmission condition to achieve seamless integrated-level solutions. Computations done within the co-design platform will also be parallelized to further provide for parameters sweeps and what-if analyses in the design cycle. Intellectual Merits The proposed research activity will lead to a seamless co-design integration platform for digital chips and RF packages. The novelties of the proposed R&D are: 1. Integration of CEM, circuit, EMC/EMI, and PCB tools through a robust and systematic domain decomposition framework; 2. Strong coupling effects, both linear and nonlinear, within different parts of the chip package will be accurately accounted for via an iteration among different simulation tools; 3. Using a novel and robust higher order Robin transmission condition, solution convergence time of the domain decomposition scheme will be significantly reduced. Broader Societal Impact The proposed parallel co-design methodology based on the domain decomposition concept addresses a crucial need for advanced microelectronic systems with numerous sensor and communication applications. The project deliverables will be made available to industrial labs via our Connection One IUCR center. This work should also allow the Center to attract new industry sponsors.