C1 Manager: Consortium Manager Account

Project: Research project

Project Details


C1 Manager: Consortium Manager Account CONNECTION ONE - TEXAS INSTRUMENTS Connection One - Qualcomm Membership Wideband Continuous Time Sigma-delta ADC for Wimax and related apps Power Scalable Digital Input Class D Audio Amplifiers with PSRR Improvement Watchdog circuit for signal processing in a radiation environment FS "Multimode-CR With Time Frequency-Based Quantifier" In this project we explore the use of a multi-phase voltage-controlled oscillator (YCO) for quantization within a continuous-time (CT) analog-to-digital converter (ADC). Fig. I illustrates a conceptual view of using a YCO, which corresponds to a multi-phase ring oscillator, to achieve quantization of an input analog voltage. The key idea is to count the number of oscillator edges that occur within each period of an input clock signal. The count values, which are digital in nature, provide a quantized estimate of the input analog voltage on according to the mapping between the tuning voltage and output frequency of the YCO. The resolution of the YCO-based quantizer is a function of the ratio of the clock period to the time spacing of the oscillator edges, which leads to a tradeoff between sample rate and the number of quantizer levels for these structures. One very interesting aspect of YCO-based quantizers is their potential ability to achieve first-order noise shaping of their quantization noise [I]. Fig. I illustrates this principle in simplified form by examining the counting process of one phase of the oscillator with a constant input. The key point here is that the truncation error at the end of a clock period boundary is not lost, but rather it is accounted for in the following measurement. Therefore, we find that the overall quantization error signal can be described by , which reveals first-order noise shaping, under the assumption that has a white noise profile. A key observation offered by Fig. 1 is that the quantization noise is first-order noise-shaped by virtue of the first-order difference operation shown in the figure, which is in agreement with the time-domain view of the quantization noise. TI - "A Combined Class-D/Class AB Audio Amplifier with Built-in DAC Channel" High efficiency audio signal chains and speaker drivers are very desirable for cellular handsets applications. Although high power efficiency of the class-D amplifiers increase the battery time, they can be sensitive to power supply variations and the suppression of distortion components at the amplifier output is minimum. Another shortcoming of class-D amplifiers is their reduced efficiency under low signal swing due to switching and conduction losses. On the other hand, class-AB linear amplifiers provide a high THO operation over a wide bandwidth. Depending on the open loop gain and signal swing, class AB amplifiers have been the choice for high efficiency headset and loudspeaker amplifiers. In this collaborative research proposal, a combined master-slave class-AB and class D audio amplifier inside a current-steering L:~ OAC is proposed. Fig. 1 shows the block diagram of the proposed master-slave linear and switch-mode combined speaker amplifier. A high GBW linear amplifier in a feedback configuration ensures that output node Vo(t) tracks the audio voltage A(t) with a closed loop gain. A low-loss current sensing circuit, high gain trans-resistance stage and synchronous rectifier forms a global feedback control loop that suppresses the current output from linear amplifier within switch-mode amplifier bandwidth. Consequently, a large portion of the load current is provided by the switch-mode amplifier. The lower efficiency linear amplifier sources small amounts of output current hn(tj to cancel out switch-mode regulator ripple, distortion components, supply noise and any undesirable high frequency content. The transient response of currents at the output of the switch-mode regulator lsn,(t), linear amplifier Inn(t) and combined master-slave supply modulator lit) is shown in Fig. 1 also. Assuming an infinite GBW linear amplifier, this architecture would generate a ripple free output current lit) to the load, while cancelling. QC - "All Digital Phase Locked Loops(ADPLL) for Process Portability and Design Re-use" The concept of All-digital PLL (ADPLL) is recently gaining interest in video communications, microprocessor clock generators and in HDD read-channel applications due to their reduced die size and fast frequency adaptation. Recently, an ADPLL has been demonstrated in a frequency synthesizer with phase noise comparable to traditional fractional-N synthesizers [2]. The main difference between a digital phase detector PLL and an ADPLL is the implementation of the loop filter and in some applications, the oscillator. Analog PLLs utilize a phase frequency detector (PFD) to measure and correct phase errors between a reference and feedback clock in a feedback configuration. An analog low-pass filter (LPF) then follows to average the PFD pulse-width modulated signal and remove any reference related harmonics. On the other hand, ADPLLs utilize a digitized version of the phase difference between the reference and feedback edges, and use minimum-phase infinite-impulse-response (IIR) digital filters for the loop filter implementation. ADPLLs can use a digital codeword controlling a digitally-controlled oscillator (DCa), or a DAC to control a VCO. As process technology shrinks transistor feature size, reduced supply voltage, wide process variations and expensive silicon estate are all contributing factors in making ADPLLs an attractive approach for wireless and wireline communication transceivers as well as microprocessor clock generation applications. Digital loop filters can enable variable loop bandwidths for the ADPlolo with minimum silicon area. The ADPlolos can be used alone or with wideband analog Pl.Ls. There are several design concerns that need to be addressed while designing ADPlolos. Due to the digitized nature of the phase detector, as in any ADC, the nonlinearity and supply rejection of this cell becomes a critical design issue. Especially in delay line based implementations, supply sensitivity of the ring-oscillator should also be minimized. In this collaborative Connection One proposal, we will develop ADPlolos utilizing all digital direct digital frequency synthesizers (phase accumulators) and frequency to digital converters (frequency discriminators) to achieve a portable, digitally intensive clock synthesizers. Drive circuits for large parallel arrays of red VCSELs Short-haul parallel optical communications for IO between integrated circuits using polymer waveguides on a printed circuit board require parallel arrays of VCSELs switching at frequencies of 1-3 GHz. To minimize power consumption, the VCSELs should emit light of a frequency with minimal transmission loss in the waveguide medium. A similar requirement exists for in-home consumer applications, where polymer fibers are more suitable than glass ones. These materials have a minimum loss near 650 nm, so red Vertical Cavity Surface Emitting Lasers (VCSELs) should be used. Red VCSELs have many other potential applications, including medical sensing and diagnostics, printing and industrial sensing. Many sensor applications typically require low noise, high analog precision drivers with feedback control to compensate for ambient and self-heating drift. We have designed and manufactured an Application Specific Integrated Circuit to capture high bandwidth signals and drive an array of VCSELs over a wide range of possible frequencies. During this project, we propose to build an optical testbed and evaluate this system in detail. II. Project Objectives a. Demonstrate 64 channel integrated ASIC and VCSEL assembly performance at a switching rate of 2 GHz. b. Quantify and model the contributions of the various noise sources in the system. c. Develop an appropriate feedback system to keep the output power of the VCSELs uniform across the 64 VCSELs in the array over duty cycle and ambient temperature. QC-All Digital Phase Locked Loops (ADPLL) for Process Portability and Design Re-Use C1-Ridgetop Group- membership account Tunable Strain Sensor with Nanoscale Resolution Based on Buckled Thin Films This project seeks to explore the application of a newly developed buckled thin film grating for high sensitivity strain sensing of semiconductor wafers. The buckled thin film grating will be attached to the wafer under study, which makes the grating periods change as the local strain changes. Such changes will be recorded with optical system, while the scanning across the sample surface will allow the 2D spatial mapping of the strain change. C1-Data Converter Designs and Reliability Investigations in Advanced CMOS Technologies ASU will conduct investigations on reliability and radiation effects in advanced CMOS technologies. In addition, ASU will develop data converters designs in these technologies. The project will be divided into two tasks: I) Advanced CMOS technology Reliability and Radiation Effects Investigations and II) Low power high speed sub sampling ADC for digital beam forming. ASU will perform the following tasks and subtasks for the program Task I: Advanced CMOS technology Reliability and Radiation Effects Investigations Subtask 1: Evaluate Ridgetop 45nm SOI chips for NBTI, HCI and/or TDDB Subtask 2: Support design of single event test structures and TID-RHBD designs for 65nm IBM tapeout. Subtask 3: Develop design equations for prognostic reliability monitors for TDDB, NBTI, PBTI, HCI, electromigration and/or TID. Deliverables: 1. Provide test plan and report on reliability effects in 45nm SOI chips . 2. Implement models of prognostic reliability monitors for TDDB, NBTI, PBTI, HCI, electromigration and/or TID in numerical simulator (e.g. TCAD) packages. Provide report on model fits to experimental data and validation of parameterized design equations. Task II: Design of the 11bit 500Msps time-interleaved sub sampling ADC Subtask 1: Design of the front-end SHA Subtask 2: Design of the time-interleaved double-sampling Pipeline ADC Subtask 3: Calibration for channel mismatch 1. Provide the following items: a. Schematics of all the circuits involved b. transistor-level simulation results including simulations across different process corners and temperature and supply voltage variation, behavioral models in Matlab/Simulink or VerilogA as required. c. Help with the RC extraction on the layout which would be mainly done at RidgeTop. 2. Progress report after completion of each subtask C1 Membership Account-Samsung Telecommunications A. The parties to this Agreement intend to join together in a cooperative effort to support an Industry/University Cooperative Research Consortium for Research and Education in Telecommunication Circuits and Systems (hereinafter called the"CENTER") at the UNIVERSITY to establish and maintain a mechanism whereby the UNIVERSITY environment will be used to undertake research and development toward the realization of enabling leading technology for the next generation of information technology and higher integration to simplify communications and enable smaller devices; B. This work will include the appropriate research in all aspects of telecommunications and information technology with an emphasis on teaching and a cooperative research program; C. The CENTER will be operated by certain designated faculty, staff and students at the UNIVERSITY. For the first five years, the CENTER will be supported jointly by private sector entities, the National Science Foundation (NSF), if NSF funds the ASU IndustrylUniversity Cooperative Research proposal (NSF 01-116), the State of Arizona, and the UNIVERSITY. Sponsor fees will be used for support of the direct and indirect costs of the CENTER. The indirect costs charged on projects is expected to be 10% - this rate is not binding and the UNIVERSITY can change to their current indirect cost rate if NSF does not join or continue funding the CENTER; and D. This program will strengthen the UNIVERSITY'S research and teaching capabilities in Telecommunication System on a Chip; Wireless Integrated Circuits and System; and Wire line and broadband communications. High Linearity, Wide Bandwidth, Envelope Tracking Regulators for Handset RF Power Amplifiers Intel Corporation. Connection One Membership Account Scaling of Inductors Towards 50um Size through Integration of Improved Magnetic Materials requirements, including 1 nH inductance at 5 GHz. Inductor scaling will be achieved by introducing magnetic materials with the optimum patterning and geometry to significantly improve ferromagnetic resonance frequency and to reduce eddy current losses. These efforts will produce inductors with much higher area efficiency and quality, enabling applications in radio frequency and analog/mixed signal circuit design, such as power amplifier, distributed wireless circuits, low noise amplifiers, high-speed signaling and clocking, which will benefit ultimately the efficient integration for System-on-Chip (SoC) and Sysem-in-Package (SiP) applications. Highly scaled inductors will greatly reduced the size of passives for interconnect and packaging applications. C1 - Qualcomm Membership Renewal All-Digital Controlled Multi-Phase DCDC Converters Overview & Work Summary: In earlier funded JPL DRDF and SURP projects, two different single stage digitally controlled DCDC converters were designed, fabricated, and tested. The first topology enabled auto tuning of the converter performance parameters by using lossless load current sensing and built-in self test functionality. The second topology reduced the analog complexity of the first revision, by using a nonlinear sliding mode controller and removing the need for PWM converter. Data Converter Designs in Advanced CMOS Technologies, Part 2 ASU will perform the following tasks and subtasks for the program Task I: Design and test of 12-bit 500Msps time-interleaved sub sampling ADC Subtask 1, MSc student 1, Fall 2012: Finalization of the digital sub-circuits Subtask 2, MSc student 2, Fall 2012: Finalization of the analog sub-circuits Subtask 3, PhD student, Spring and Summer 2013: Silicon-validate functionality and performance of ADC chips Deliverables: 1. Provide the following items: a. Schematics of all the circuits involved b. Transistor-level simulation results including simulations across different process corners and temperature and supply voltage variation, behavioral models in Matlab/Simulink or VerilogA as required. c. Perform RC extraction on the layout which will be prepared by RidgeTop. d. Silicon-validation test results 2. Progress report after completion of each subtask Probabilistic Fatigue Life Prediction and Risk Assessment of Aging Bridges in Cold Regions Statement of Work at ASU Objectives The overall goal of the proposed project is to develop, validate and demonstrate a general damage growth and risk assessment methodology for aging bridges in cold regions. Five major objectives are identified: (1) Develop a general life prediction methodology for aging bridges considering small crack growth behavior and multiaxial cyclic load; (2) Develop a general methodology to include corrosion effect on the probabilistic life prediction of aging bridges in cold regions; (3) Develop a general random process representation of fatigue damage accumulation using Karhunen-Loeve expansion technique; (4) Develop and implement a methodology for multi-scale (material, component, and structure) reliability evaluation using both analytical and numerical simulation technique; (5) Develop a systematically integrated educational plan based on the proposed research activities and outcomes to improve both undergraduate and graduate curriculums at Clarkson University. CONNECTION ONE PROJECT ACCOUNT: Fast Solvent Recharge using Porous Gels for Cooling Digital LDO This work is the development and system analysis of a fully digitally controlled low dropout linear voltage regulator (LDO). Dr. Kiaei and of his students will work on the system design, circuits and simulation of digital LDO. The funds will be used to support the student for six months. There will be monthly calls and quarterly visits to Intel to discuss the project. This project will be a Connection One core-project. C1 Membership Account: NXP Semiconductors USA, Inc. CONNECTION ONE PROJECT ACCOUNT: Tunable Strain Sensor with Nanoscale Resolution Based on Buckled Thin Films This project seeks to explore the application of a newly developed buckled thin film grating for high sensitivity strain sensing of microelectronic packages and extending to backend films in semiconductor wafers. The grating will be directly fabricated on the packages under study, which makes the grating periods change as the local strain changes. Such changes will be recorded with optical system, while the scanning across the sample surface will allow the 2D spatial mapping of the strain change. Problems to be addressed: Fill the gap of Intels in-plane strain measurement metrology roadmap in sub-micron regime Enable better understanding of Silicon backend, FLI, passives and package substrate response; and serve as a validation tool for numerical analysis involving these areas Prepare Intel for mechanical characterization of future advanced package technologies Objective Find a low-cost, largely scalable (size and shape) measurement solution for nano-scale deformation based on thin film buckling behavior C1 Project Acct SM - System Identification, Diagnosis, and Built-In-Self-Test of High Switching Rate DC-DC Converters Summary/Research Scope: High efficiency power converters are an essential part of space communication modules. Their applications range from RF transceivers, to RF PAs, and analog baseband strip. The DCDC converters are used across a large set of environmental and load conditions, and their performance degrade with aging and environmental effects. As an example, LCR of the DC-DC converters degrade over time and usage, as well as the MOSFETS making up the power train age and will not give optimized output with a classical controller. High speed converters have smaller component sizing, faster settling time, but the their converter loop dynamics are sensitive to external LC and R variations. Converter performance is also affected by manufacturing tolerances and parasitics. In this project, several techniques for on-line system identification, self-test and diagnosis of DCDC converters will be developed. Using white noise based stimulus, the system will be diagnosed while operating in a closed loop configuration, without the need for open-loop characterization. Successful outcome of this will enable logging of diagnostics of the converter and/or self-tuning of the controller to overcome the aging effects in harsh environments. C1 Project Acct QC: Digital Intensive PLLs for RF Applications
Effective start/end date7/1/078/31/14


  • INDUSTRY: Various Consortium Members: $1,437,234.00


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