Air Option 1: Technology Translation - Compiler Technology for Modern Manycore Architectures

Project: Research project

Project Details

Description

As the number of cores scale, scaling the memory architecture is a major challenge. Data and communication management functionality is expected to migrate from hardware (in existing technology) to software domain. We have developed compiler technology that will enable simple multicore processors, without memory management in hardware, to execute traditional applications that will be (and are being) developed for processors with memory management in hardware. In this PFI-AIR proposal, we propose to translate our compiler technology into a general purpose compiler solution, by implementing the same on a portable and re-targetable compiler framework - LLVM, that has now become the industry standard. We propose to build a proof-of-concept compiler on LLVM, for an ARM based embedded architecture (which currently consists of an under-used scratch-pad memory along with a cache), and demonstrate the applicability of our solution for modern and possibly near-future many-core processor designs (with only the software controlled scratch-pad memory). In our talks with some of the processor design companies (including Intel), they have already mentioned the difficulty they are facing in developing coherent cache multicore architectures, and the problems only increase as we scale the number of cores. They claim that if we can manage all these things in software, they can save a lot of design time and effort. As part of market research, we plan to conduct talks with more processor design companies, including IBM, Cisco, TI and find their challenges, and get to know their roadmap for future processors. We can then tune our compiler to their flavor of (or rather lack of) memory management, and develop software development tools, including the compiler for such future many-core processor architectures. Software developers, and embedded application developers, that want to exploit the most power and performance efficient computing processor for their designs, will benefit from this innovation. Without our compiler solution, they will not be able to execute existing programs on near-future multicores, and will have to do a very significant re-write of their applications, which will be quite tricky and inefficient. Our compiler solution can thus accelerate innovation in both software application development, and processor architecture design, towards building an extremely low power and high-performance computing solution.

Description

Project Summary As technology scales, the number of cores in processors will rapidly increase in order to avoid the power wall. In processors that have hundreds and thousands of cores, traditional memory architectures { in which a coherent memory interface is provided to all the cores in hardware, will not be feasible. The memory management functionality is expected to migrate from hardware (in existing systems) to the software domain. As a result, existing programs { that have been written assuming that processor hardware will provide memory management support { will not execute correctly on these modern many-core architectures. To make existing programs run correctly on such modern many-core architectures, programmers will have to manually change the program by inserting memory management functionality in the program. However, this is extremely dicult, and even if possible, manual memory management is tedious and a highly error-prone process. The proposed compiler relieves the programmer of this eort and pain by performing correct and ecient memory management automatically. System development companies that use relatively high-performance computing capabilities will need this compiler solution. There are many such companies: e.g., Raytheon that develop defense and surveillance systems that require high degrees of computation, Honeywell that develops medical devices such as 3D topographers, etc. This compiler technology can provide them with the power and performance edge that their applications need, and improve the end user's experience in terms of, better response time of applications (higher performance), and smaller battery charging time, and reduced charging frequency, and lower device weight (lower power).
StatusFinished
Effective start/end date9/15/132/29/16

Funding

  • National Science Foundation (NSF): $150,000.00

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