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Research Output 2007 2019

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2019

A 1.06-μW Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring

Yin, S., Kim, M., Kadetotad, D., Liu, Y., Bae, C., Kim, S. J., Cao, Y. & Seo, J., Aug 1 2019, In : IEEE Journal of Solid-State Circuits. 54, 8, p. 2316-2326 11 p., 8713394.

Research output: Contribution to journalArticle

Biometrics
Electrocardiography
Authentication
Monitoring
Neural networks

Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview

Chen, C. Y., Murmann, B., Seo, J. & Yoo, H. J., Jun 1 2019, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 9, 2, p. 247-252 6 p., 8720273.

Research output: Contribution to journalArticle

Networks (circuits)
Learning algorithms
Demonstrations
Hardware
Deep learning
2018
12 Citations (Scopus)

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler

Ma, Y., Suda, N., Cao, Y., Vrudhula, S. & Seo, J., Jan 1 2018, (Accepted/In press) In : Integration, the VLSI Journal.

Research output: Contribution to journalArticle

Learning algorithms
Field programmable gate arrays (FPGA)
Neural networks
Throughput
Hardware
Particle accelerators
Field programmable gate arrays (FPGA)
Neural networks
Hardware
Complex networks
10 Citations (Scopus)

Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions

Basu, A., Acharya, J., Karnik, T., Liu, H., Li, H., Seo, J. & Song, C., Mar 14 2018, (Accepted/In press) In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Research output: Contribution to journalArticle

Adaptive systems
Memristors
Hardware
Magnetoelectronics
Networks (circuits)
9 Citations (Scopus)
Convolution
Field programmable gate arrays (FPGA)
Neural networks
Particle accelerators
Hardware
Speech recognition
Hardware
Energy efficiency
Application specific integrated circuits
Deep neural networks

Process Scalability of Pulse-Based Circuits for Analog Image Convolution

D'Angelo, R., Du, X., Salthouse, C. D., Hollosi, B., Freifeld, G., Uy, W., Huang, H., Tran, N., Chery, A., Seo, J., Cao, Y., Poppe, D. C. & Sonkusale, S. R., Apr 19 2018, (Accepted/In press) In : IEEE Transactions on Circuits and Systems I: Regular Papers.

Research output: Contribution to journalArticle

Convolution
Scalability
Networks (circuits)
Computer vision
Neurons
2017

Improving efficiency in sparse learning with the feedforward inhibitory motif

Xu, Z., Skorheim, S., Tu, M., Berisha, V., Yu, S., Seo, J., Bazhenov, M. & Cao, Y., Feb 11 2017, (Accepted/In press) In : Neurocomputing.

Research output: Contribution to journalArticle

Neural Networks (Computer)
Learning
Efficiency
Neural networks
Neurology
6 Citations (Scopus)

Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities

Li, J., Seo, J., Kymissis, I. & Seok, M., Oct 1 2017, In : IEEE Journal of Solid-State Circuits. 52, 10, p. 2550-2562 13 p., 8030042.

Research output: Contribution to journalArticle

Energy harvesting
Conversion efficiency
Capacitors
Secondary batteries
Photovoltaic cells
2016
1 Citation (Scopus)

A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware

Shah, M., Arunachalam, S., Wang, J., Blaauw, D., Sylvester, D., Kim, H. S., Seo, J. & Chakrabarti, C., Nov 25 2016, (Accepted/In press) In : Journal of Signal Processing Systems. p. 1-15 15 p.

Research output: Contribution to journalArticle

Network Architecture
Network architecture
Speech recognition
Computer hardware
Speech Recognition
9 Citations (Scopus)

A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering

Bang, S., Seo, J., Chang, L., Blaauw, D. & Sylvester, D., Jan 20 2016, (Accepted/In press) In : IEEE Journal of Solid-State Circuits.

Research output: Contribution to journalArticle

Voltage regulators
Capacitors
Capacitance
Modulation
Controllers
11 Citations (Scopus)

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Kulkarni, N., Yang, J., Seo, J. & Vrudhula, S., Mar 10 2016, (Accepted/In press) In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Research output: Contribution to journalArticle

Threshold logic
Flip flop circuits
Application specific integrated circuits
Logic gates
Networks (circuits)
2015
38 Citations (Scopus)

Fully parallel write/read in resistive synaptic array for accelerating on-chip learning

Gao, L., Wang, I. T., Chen, P. Y., Vrudhula, S., Seo, J., Cao, Y., Hou, T. H. & Yu, S., Oct 22 2015, In : Nanotechnology. 26, 45, 455204.

Research output: Contribution to journalArticle

Silicon
Learning algorithms
Energy efficiency

Fully parallel write/read in resistive synaptic array for accelerating on-chip learning

Gao, L., Wang, I. T., Chen, P. Y., Vrudhula, S., Seo, J. S., Cao, Y., Hou, T. H. & Yu, S., Nov 13 2015, In : Nanotechnology. 26, 45, p. 455204 1 p.

Research output: Contribution to journalArticle

Learning
Equipment and Supplies
Silicon
Learning algorithms
Energy efficiency
11 Citations (Scopus)

On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices

Seo, J., Lin, B., Kim, M., Chen, P. Y., Kadetotad, D., Xu, Z., Mohanty, A., Vrudhula, S., Yu, S., Ye, J. & Cao, Y., Nov 1 2015, In : IEEE Transactions on Nanotechnology. 14, 6, p. 969-979 11 p., 7268884.

Research output: Contribution to journalArticle

CMOS integrated circuits
Parallel architectures
Application specific integrated circuits
Program processors
Glossaries
28 Citations (Scopus)

Parallel architecture with resistive crosspoint array for dictionary learning acceleration

Kadetotad, D., Xu, Z., Mohanty, A., Chen, P. Y., Lin, B., Ye, J., Vrudhula, S., Yu, S., Cao, Y. & Seo, J., Jun 1 2015, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 5, 2, p. 194-204 11 p., 07116611.

Research output: Contribution to journalArticle

Parallel architectures
Glossaries
Data storage equipment
Computer peripheral equipment
Networks (circuits)
2013
94 Citations (Scopus)

Specifications of nanoscale devices and circuits for neuromorphic computational systems

Rajendran, B., Liu, Y., Seo, J., Gopalakrishnan, K., Chang, L., Friedman, D. J. & Ritter, M. B., 2013, In : IEEE Transactions on Electron Devices. 60, 1, p. 246-253 8 p., 6374663.

Research output: Contribution to journalArticle

Specifications
Networks (circuits)
Neurons
Learning systems
Brain
2011
7 Citations (Scopus)

A robust edge encoding technique for energy-efficient multi-cycle interconnect

Seo, J., Kaul, H., Krishnamurthy, R., Sylvester, D. & Blaauw, D., Feb 2011, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19, 2, p. 264-273 10 p., 5286242.

Research output: Contribution to journalArticle

Energy utilization
Energy conservation
Capacitance
Throughput
Networks (circuits)
9 Citations (Scopus)

Crosstalk-aware PWM-based on-chip links with self-calibration in 65 nm CMOS

Seo, J., Blaauw, D. & Sylvester, D., Sep 2011, In : IEEE Journal of Solid-State Circuits. 46, 9, p. 2041-2052 12 p., 5766781.

Research output: Contribution to journalArticle

Crosstalk
Pulse width modulation
Telecommunication links
Calibration
Telecommunication repeaters
2009
23 Citations (Scopus)

A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s logarithmic pipeline ADC

Lee, J., Kang, J., Park, S., Seo, J., Anders, J., Guilherme, J. & Flynn, M. P., Oct 2009, In : IEEE Journal of Solid-State Circuits. 44, 10, p. 2755-2765 11 p., 18.

Research output: Contribution to journalArticle

Digital to analog conversion
Pipelines
Capacitors
2008
6 Citations (Scopus)

Self-timed regenerators for high-speed and low-power on-chip global interconnect

Singh, P., Seo, J., Blaauw, D. & Sylvester, D., Jun 2008, In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 6, p. 673-677 5 p., 4511670.

Research output: Contribution to journalArticle

Regenerators
Wire
Telecommunication repeaters
Clock distribution networks
Networks (circuits)