Jae-sun Seo

Asst Professor

  • 1160 Citations
  • 16 h-Index
20072022
If you made any changes in Pure, your changes will be visible here soon.

Research Output 2007 2019

2019

A 1.06-μW Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring

Yin, S., Kim, M., Kadetotad, D., Liu, Y., Bae, C., Kim, S. J., Cao, Y. & Seo, J., Aug 1 2019, In : IEEE Journal of Solid-State Circuits. 54, 8, p. 2316-2326 11 p., 8713394.

Research output: Contribution to journalArticle

Biometrics
Electrocardiography
Authentication
Monitoring
Neural networks

Cases for analog mixed signal computing integrated circuits for deep neural networks

Seok, M., Yang, M., Jiang, Z., Lazar, A. A. & Seo, J., Apr 1 2019, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8742044. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

integrated circuits
Integrated circuits
emerging
hybrid circuits
analogs

Corrigendum: Large-scale neuromorphic spiking array processors: A quest to mimic the brain (Frontiers in Neuroscience (2018) 12 (891) DOI: 10.3389/fnins.2018.00891)

Thakur, C. S., Molin, J. L., Cauwenberghs, G., Indiveri, G., Kumar, K., Qiao, N., Schemmel, J., Wang, R., Chicca, E., Hasler, J. O., Seo, J., Yu, S., Cao, Y., Van Schaik, A. & Etienne-Cummings, R., Jan 1 2019, In : Frontiers in Neuroscience. 13, JAN, 991.

Research output: Contribution to journalComment/debate

Open Access
Neurosciences
Neurons
Neuronal Plasticity
Brain
corrigendum

Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview

Chen, C. Y., Murmann, B., Seo, J. & Yoo, H. J., Jun 1 2019, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 9, 2, p. 247-252 6 p., 8720273.

Research output: Contribution to journalArticle

Networks (circuits)
Learning algorithms
Demonstrations
Hardware
Deep learning

Joint Optimization of Quantization and Structured Sparsity for Compressed Deep Neural Networks

Srivastava, G., Kadetotad, D., Yin, S., Berisha, V., Chakrabarti, C. & Seo, J., May 1 2019, 2019 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2019 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 1393-1397 5 p. 8682791. (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings; vol. 2019-May).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Deep neural networks
Degradation
2018
13 Citations (Scopus)

ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler

Ma, Y., Suda, N., Cao, Y., Vrudhula, S. & Seo, J., Jan 1 2018, (Accepted/In press) In : Integration, the VLSI Journal.

Research output: Contribution to journalArticle

Learning algorithms
Field programmable gate arrays (FPGA)
Neural networks
Throughput
Hardware
1 Citation (Scopus)

Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations

Yin, S., Venkataramanaiah, S. K., Chen, G. K., Krishnamurthy, R., Cao, Y., Chakrabarti, C. & Seo, J., Mar 23 2018, 2017 IEEE Biomedical Circuits and Systems Conference, BioCAS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1-4 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

spiking
Backpropagation
hardware
Chemical activation
activation

Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs

Ma, Y., Zheng, T., Cao, Y., Vrudhula, S. & Seo, J., Nov 5 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2018 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., a57

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Detectors
Hardware
Image classification
Digital circuits

A Parallel RRAM Synaptic Array Architecture for Energy-Efficient Recurrent Neural Networks

Yin, S., Sun, X., Yu, S., Seo, J. & Chakrabarti, C., Dec 31 2018, Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2018. Institute of Electrical and Electronics Engineers Inc., p. 13-18 6 p. 8598445. (IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation; vol. 2018-October).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Recurrent neural networks
XNOR
Recurrent Neural Networks
Energy Efficient
Activation
Particle accelerators
Field programmable gate arrays (FPGA)
Neural networks
Hardware
Complex networks
10 Citations (Scopus)

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons

Sun, X., Peng, X., Chen, P. Y., Liu, R., Seo, J. & Yu, S., Feb 20 2018, ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 574-579 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Neurons
Neural networks
Network architecture
Energy efficiency
Parallel architectures

Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms

Basu, A., Chang, M. F., Chicca, E., Karnik, T., Li, H. & Seo, J., Mar 1 2018, In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 8, 1, p. 1-5 5 p.

Research output: Contribution to journalEditorial

Adaptive systems
Networks (circuits)

Guest editors' introduction: Frontiers of hardware and algorithms for on-chip learning

Cao, Y., Li, X., Seo, J. & Dasika, G., Jul 1 2018, In : ACM Journal on Emerging Technologies in Computing Systems. 14, 2, 3205944.

Research output: Contribution to journalEditorial

Hardware
11 Citations (Scopus)

Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions

Basu, A., Acharya, J., Karnik, T., Liu, H., Li, H., Seo, J. & Song, C., Mar 14 2018, (Accepted/In press) In : IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Research output: Contribution to journalArticle

Adaptive systems
Memristors
Hardware
Magnetoelectronics
Networks (circuits)
1 Citation (Scopus)

Minimizing area and energy of deep learning hardware design using collective low precision and structured compression

Yin, S., Srivastava, G., Venkataramanaiah, S. K., Chakrabarti, C., Berisha, V. & Seo, J., Apr 10 2018, Conference Record of 51st Asilomar Conference on Signals, Systems and Computers, ACSSC 2017. Matthews, M. B. (ed.). Institute of Electrical and Electronics Engineers Inc., Vol. 2017-October. p. 1907-1911 5 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware Design
learning
hardware
Compression
Neural Networks
11 Citations (Scopus)
Convolution
Field programmable gate arrays (FPGA)
Neural networks
Particle accelerators
Hardware
Speech recognition
Hardware
Energy efficiency
Application specific integrated circuits
Deep neural networks

Process Scalability of Pulse-Based Circuits for Analog Image Convolution

D'Angelo, R., Du, X., Salthouse, C. D., Hollosi, B., Freifeld, G., Uy, W., Huang, H., Tran, N., Chery, A., Seo, J., Cao, Y., Poppe, D. C. & Sonkusale, S. R., Apr 19 2018, (Accepted/In press) In : IEEE Transactions on Circuits and Systems I: Regular Papers.

Research output: Contribution to journalArticle

Convolution
Scalability
Networks (circuits)
Computer vision
Neurons
3 Citations (Scopus)

Random sparse adaptation for accurate inference with inaccurate multi-level RRAM arrays

Mohanty, A., Du, X., Chen, P. Y., Seo, J., Yu, S. & Cao, Y., Jan 23 2018, 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., Vol. Part F134366. p. 6.3.1-6.3.4

Research output: Chapter in Book/Report/Conference proceedingConference contribution

inference
cells
education
Data storage equipment
learning

Towards a Wearable Cough Detector Based on Neural Networks

Kadambi, P., Mohanty, A., Ren, H., Smith, J., McGuinnes, K., Holt, K., Furtwaengler, A., Slepetys, R., Yang, Z., Seo, J., Chae, J., Cao, Y. & Berisha, V., Sep 10 2018, 2018 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-April. p. 2161-2165 5 p. 8461394

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Microphones
Audio recordings
Detectors
Neural networks
Pulmonary diseases

Well-Posed Verilog-A Compact Model for Phase Change Memory

Kulkarni, S. R., Kadetotad, D. V., Seo, J. & Rajendran, B., Nov 28 2018, SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-September. p. 369-373 5 p. 8551667

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Phase change memory
Computer hardware description languages
Phase Change
Data storage equipment
Computer programming
19 Citations (Scopus)

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks

Sun, X., Yin, S., Peng, X., Liu, R., Seo, J. & Yu, S., Apr 19 2018, Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1423-1428 6 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Neural networks
Convolution
Energy efficiency
RRAM
Chemical activation
10 Citations (Scopus)

XNOR-SRAM: In-memory computing SRAM macro for binary/ternary deep neural networks

Jiang, Z., Yin, S., Seok, M. & Seo, J., Oct 25 2018, 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-June. p. 173-174 2 p. 8510687

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Static random access storage
Macros
Data storage equipment
Application specific integrated circuits
Deep neural networks
2017
6 Citations (Scopus)

A 1.06 μw smart ECG processor in 65 nm CMOS for real-time biometrie authentication and personal cardiac monitoring

Yin, S., Kim, M., Kadetotad, D., Liu, Y., Bae, C., Kim, S. J., Cao, Y. & Seo, J., Aug 10 2017, 2017 Symposium on VLSI Circuits, VLSI Circuits 2017. Institute of Electrical and Electronics Engineers Inc., p. C102-C103 8008563

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Authentication
Monitoring
Biometrics
Neural networks
alachlor
25 Citations (Scopus)

An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks

Ma, Y., Cao, Y., Vrudhula, S. & Seo, J., Oct 2 2017, 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017. Institute of Electrical and Electronics Engineers Inc., 8056824

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Throughput
Neural networks
Hardware
Particle accelerators

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS

Kim, M., Mohanty, A., Kadetotad, D., Suda, N., Wei, L., Saseendran, P., He, X., Cao, Y. & Seo, J., Sep 25 2017, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050798

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
Traffic signs
Electric power utilization
Classifiers
Color

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS

Kim, M., Mohanty, A., Kadetotad, D., Suda, N., Wei, L., Saseendran, P., He, X., Cao, Y. & Seo, J., Feb 16 2017, 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., p. 21-22 2 p. 7858282

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Traffic signs
Particle accelerators
Classifiers
Color
Object detection
2 Citations (Scopus)

Bi-Level rare temporal pattern detection

Zhou, D., He, J., Cao, Y. & Seo, J., Jan 31 2017, Proceedings - 16th IEEE International Conference on Data Mining, ICDM 2016. Institute of Electrical and Electronics Engineers Inc., p. 719-728 10 p. 7837896

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electrocardiography
Sensor networks
Labels
Wireless networks

Comprehensive evaluation of openCL-based CNN implementations for FPGAs

Tapiador-Morales, R., Rios-Navarro, A., Linares-Barranco, A., Kim, M., Kadetotad, D. & Seo, J., 2017, Advances in Computational Intelligence - 14th International Work-Conference on Artificial Neural Networks, IWANN 2017, Proceedings. Springer Verlag, Vol. 10306 LNCS. p. 271-282 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 10306 LNCS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Comprehensive Evaluation
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Neural Networks
Neural networks
1 Citation (Scopus)

Designing ECG-based physical unclonable function for security of wearable devices

Yin, S., Bae, C., Kim, S. J. & Seo, J., Sep 13 2017, 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society: Smarter Technology for a Healthier World, EMBC 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 3509-3512 4 p. 8037613

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Electrocardiography
Equipment and Supplies
Hamming distance
Biometric Identification
Computer Security
14 Citations (Scopus)

End-to-end scalable FPGA accelerator for deep residual networks

Ma, Y., Kim, M., Cao, Y., Vrudhula, S. & Seo, J., Sep 25 2017, IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 8050344

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Particle accelerators
Field programmable gate arrays (FPGA)
Hardware
Image recognition
Learning algorithms
1 Citation (Scopus)

Flying and decoupling capacitance optimization for area-constrained on-chip switched-capacitor voltage regulators

Mi, X., Moghadam, H. F. & Seo, J., May 11 2017, Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. Institute of Electrical and Electronics Engineers Inc., p. 1269-1272 4 p. 7927186

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Voltage regulators
Capacitors
Capacitance
Electric potential

Improving efficiency in sparse learning with the feedforward inhibitory motif

Xu, Z., Skorheim, S., Tu, M., Berisha, V., Yu, S., Seo, J., Bazhenov, M. & Cao, Y., Feb 11 2017, (Accepted/In press) In : Neurocomputing.

Research output: Contribution to journalArticle

Neural Networks (Computer)
Learning
Efficiency
Neural networks
Neurology
2 Citations (Scopus)

Low-power neuromorphic speech recognition engine with coarse-grain sparsity

Yin, S., Kadetotad, D., Yan, B., Song, C., Chen, Y., Chakrabarti, C. & Seo, J., Feb 16 2017, 2017 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017. Institute of Electrical and Electronics Engineers Inc., p. 111-114 4 p. 7858305

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Speech recognition
Engines
Data storage equipment
Particle accelerators
Hardware
4 Citations (Scopus)

Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition

Chang, K., Kadetotad, D., Cao, Y., Seo, J. & Lim, S. K., Aug 11 2017, ISLPED 2017 - IEEE/ACM International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 8009175

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Speech recognition
Hardware
Energy efficiency
Application specific integrated circuits
Integrated circuit design
68 Citations (Scopus)

Optimizing loop operation and dataflow in FPGA acceleration of deep convolutional neural networks

Ma, Y., Cao, Y., Vrudhula, S. & Seo, J., Feb 22 2017, FPGA 2017 - Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. Association for Computing Machinery, Inc, p. 45-54 10 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Field programmable gate arrays (FPGA)
Neural networks
Convolution
Particle accelerators
Hardware
6 Citations (Scopus)

Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities

Li, J., Seo, J., Kymissis, I. & Seok, M., Oct 1 2017, In : IEEE Journal of Solid-State Circuits. 52, 10, p. 2550-2562 13 p., 8030042.

Research output: Contribution to journalArticle

Energy harvesting
Conversion efficiency
Capacitors
Secondary batteries
Photovoltaic cells
1 Citation (Scopus)

Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability

Li, J., Seo, J., Kymissis, I. & Seok, M., Feb 6 2017, 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 289-292 4 p. 7844192

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Conversion efficiency
Energy dissipation
Secondary batteries
Photovoltaic cells
Energy harvesting
2016
1 Citation (Scopus)

A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware

Shah, M., Arunachalam, S., Wang, J., Blaauw, D., Sylvester, D., Kim, H. S., Seo, J. & Chakrabarti, C., Nov 25 2016, (Accepted/In press) In : Journal of Signal Processing Systems. p. 1-15 15 p.

Research output: Contribution to journalArticle

Network Architecture
Network architecture
Speech recognition
Computer hardware
Speech Recognition
11 Citations (Scopus)

A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering

Bang, S., Seo, J., Chang, L., Blaauw, D. & Sylvester, D., Jan 20 2016, (Accepted/In press) In : IEEE Journal of Solid-State Circuits.

Research output: Contribution to journalArticle

Voltage regulators
Capacitors
Capacitance
Modulation
Controllers
9 Citations (Scopus)

Compact oscillation neuron exploiting metal-insulator-transition for neuromorphic computing

Chen, P. Y., Seo, J., Cao, Y. & Yu, S., Nov 7 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2016. Institute of Electrical and Electronics Engineers Inc., Vol. 07-10-November-2016. 2967015

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Metal insulator transition
Neurons
Transistors
Computer peripheral equipment
Resistors
9 Citations (Scopus)

Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications

Kadetotad, D., Arunachalam, S., Chakrabarti, C. & Seo, J., Nov 7 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2016. Institute of Electrical and Electronics Engineers Inc., Vol. 07-10-November-2016. 2967028

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Data storage equipment
Speech recognition
Hardware
Neurons
Network layers
6 Citations (Scopus)

High-performance face detection with CPU-FPGA acceleration

Mohanty, A., Suda, N., Kim, M., Vrudhula, S., Seo, J. & Cao, Y., Jul 29 2016, ISCAS 2016 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-July. p. 117-120 4 p. 7527184

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Face recognition
Program processors
Field programmable gate arrays (FPGA)
Data storage equipment
Security of data
55 Citations (Scopus)

Mitigating effects of non-ideal synaptic device characteristics for on-chip learning

Chen, P. Y., Lin, B., Wang, I. T., Hou, T. H., Ye, J., Vrudhula, S., Seo, J., Cao, Y. & Yu, S., Jan 5 2016, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., p. 194-199 6 p. 7372570

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Learning algorithms
Calibration
3 Citations (Scopus)

Nanoelectronic neurocomputing: Status and prospects

Ceze, L., Hasler, J., Likharev, K. K., Seo, J., Sherwood, T., Strukov, D., Xie, Y. & Yu, S., Aug 22 2016, 74th Annual Device Research Conference, DRC 2016. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-August. 7548506

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nanoelectronics
Digital circuits
Convolution
Learning systems
Electric power utilization
3 Citations (Scopus)

Ranking the parameters of deep neural networks using the fisher information

Tu, M., Berisha, V., Woolf, M., Seo, J. & Cao, Y., May 18 2016, 2016 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2016 - Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2016-May. p. 2647-2651 5 p. 7472157

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Accelerometers
Field programmable gate arrays (FPGA)
Deep neural networks
11 Citations (Scopus)

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Kulkarni, N., Yang, J., Seo, J. & Vrudhula, S., Mar 10 2016, (Accepted/In press) In : IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Research output: Contribution to journalArticle

Threshold logic
Flip flop circuits
Application specific integrated circuits
Logic gates
Networks (circuits)

Reducing the model order of deep neural networks using information theory

Tu, M., Berisha, V., Cao, Y. & Seo, J., Sep 2 2016, Proceedings - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016. IEEE Computer Society, Vol. 2016-September. p. 93-98 6 p. 7560179

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Information theory
Redundancy
Neural networks
Deep neural networks
43 Citations (Scopus)

Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA

Ma, Y., Suda, N., Cao, Y., Seo, J. & Vrudhula, S., Sep 26 2016, FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications. Institute of Electrical and Electronics Engineers Inc., 7577356

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Compilation
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Neural Networks
Neural networks
5 Citations (Scopus)

Thermoelectric-based sustainable self-cooling for fine-grained processor hot spots

Lee, S., Pandiyan, D., Seo, J., Phelan, P. & Wu, C-J., Jul 20 2016, Proceedings of the 15th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2016. Institute of Electrical and Electronics Engineers Inc., p. 847-856 10 p. 7517635

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cooling
Temperature
Waste heat
Heat sinks
Fans