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Fingerprint Dive into the research topics where Jae-sun Seo is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

  • 8 Similar Profiles
Hardware Engineering & Materials Science
Data storage equipment Engineering & Materials Science
Neural networks Engineering & Materials Science
Field programmable gate arrays (FPGA) Engineering & Materials Science
Networks (circuits) Engineering & Materials Science
Particle accelerators Engineering & Materials Science
Learning algorithms Engineering & Materials Science
Neurons Engineering & Materials Science

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Research Output 2007 2019

A 1.06-μW Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring

Yin, S., Kim, M., Kadetotad, D., Liu, Y., Bae, C., Kim, S. J., Cao, Y. & Seo, J. S., Aug 1 2019, In : IEEE Journal of Solid-State Circuits. 54, 8, p. 2316-2326 11 p., 8713394.

Research output: Contribution to journalArticle

Biometrics
Electrocardiography
Authentication
Monitoring
Neural networks

A 8.93-TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity with All Parameters Stored On-Chip

Kadetotad, D., Berisha, V., Chakrabarti, C. & Seo, J. S., Sep 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., p. 119-122 4 p. 8902809. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TOPS (spacecraft)
Recurrent neural networks
Particle accelerators
accelerators
chips

A Real-Time 17-Scale Object Detection Accelerator with Adaptive 2000-Stage Classification in 65 nm CMOS

Kim, M., Mohanty, A., Kadetotad, D., Wei, L., He, X., Cao, Y. & Seo, J. S., Oct 2019, In : IEEE Transactions on Circuits and Systems I: Regular Papers. 66, 10, p. 3843-3853 11 p., 8741167.

Research output: Contribution to journalArticle

Particle accelerators
Application specific integrated circuits
Hardware
Learning systems
Traffic signs

C3SRAM: In-Memory-Computing SRAM Macro Based on Capacitive-Coupling Computing

Jiang, Z., Yin, S., Seo, J. S. & Seok, M., Sep 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., p. 131-134 4 p. 8902752. (ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TOPS (spacecraft)
Static random access storage
multiplication
Macros
central processing units

Cases for analog mixed signal computing integrated circuits for deep neural networks

Seok, M., Yang, M., Jiang, Z., Lazar, A. A. & Seo, J., Apr 1 2019, 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019. Institute of Electrical and Electronics Engineers Inc., 8742044. (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

integrated circuits
Integrated circuits
emerging
hybrid circuits
analogs

Projects 2015 2022